Flash Memory Integration in FDSOI Substrates
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Solution Overview
Problem
The integration of flash memory devices in CMOS technologies, particularly in Fully Depleted Silicon-On-Insulator (FDSOI) manufacturing, requires additional deposition and masking steps, increasing complexity and costs due to the need for co-integration with field effect transistors.
Innovation Solution
A manufacturing technique that integrates flash memory devices within the FDSOI process flow by using a silicon-on-insulator (SOI) substrate with a buried oxide layer and a semiconductor layer, forming flash and read transistors with a floating gate and control gate, and reducing the number of processing steps through optimized layer formation and masking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory devices are integrated in FDSOI manufacturing with conventional co-integration methods, then both flash memory and FETs can be manufactured on the same substrate, but the number of additional deposition and masking steps increases, leading to increased complexity and costs
Solution Approach 1:
The patent merges the flash memory fabrication process with the FDSOI CMOS process flow by using a shared semiconductor layer. The semiconductor layer serves dual purposes: as the channel for FDSOI transistors in logic regions and as the floating gate for flash memory cells in memory regions. This consolidation eliminates the need for separate floating gate formation steps and reduces the number of masking operations required for co-integration.
Solution Approach 2:
The semiconductor layer is designed to perform multiple functions depending on the region: it acts as the active channel for FDSOI transistors in logic areas and as the floating gate structure for flash memory in memory areas. This multi-functionality allows a single layer to serve both device types, reducing overall process complexity and the number of additional steps needed for co-integration.
2Adaptability or versatility
If flash memory devices are integrated in FDSOI manufacturing with conventional co-integration methods, then both flash memory and FETs can be manufactured on the same substrate, but manufacturing costs increase due to additional processing steps
Solution Approach 1:
The patent merges the flash memory fabrication process with the FDSOI CMOS process flow by using a shared semiconductor layer. The semiconductor layer serves dual purposes: as the channel for FDSOI transistors in logic regions and as the floating gate for flash memory cells in memory regions. This consolidation eliminates the need for separate floating gate formation steps and reduces the number of masking operations required for co-integration.
Solution Approach 2:
The semiconductor layer is designed to perform multiple functions depending on the region: it acts as the active channel for FDSOI transistors in logic areas and as the floating gate structure for flash memory in memory areas. This multi-functionality allows a single layer to serve both device types, reducing overall process complexity and the number of additional steps needed for co-integration.
Data Source
AI summary
An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.