Flash Memory Forward Error Correction with Parallel Detection

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Solution Overview

Problem

Flash memory technologies face challenges in maintaining high reliability and longevity due to data retention and corruption issues caused by bit errors, which existing error correction methods struggle to address effectively, especially as storage density increases.

Innovation Solution

Implementing a forward error correction system that dynamically adapts coding rates and allocates error correction resources based on age and error rates, using parallel error detection and correction modules to process data streams and dynamically reassigning resources across flash memory sectors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If storage density is increased in flash memory, then storage capacity increases and cost decreases, but error rate increases making data retention and corruption more likely

Engineering Contradiction:
Improvestorage capacityVSAvoiddata retention
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The flash memory system is divided into multiple sectors, each with dedicated error detection and correction sub-modules. This segmentation allows independent error handling for each sector, enabling the system to maintain high storage density while providing targeted error correction where needed, thus preserving data retention reliability despite increased overall capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically adapts coding rates based on monitored error rates and sector age. As flash memory cells degrade over time or accumulate errors, the system increases the coding rate (adds more redundancy) for affected sectors. This parameter change allows the system to maintain reliable data retention even as storage density increases and inherent error rates rise.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If error correction resources are increased to handle higher error rates, then data integrity improves, but device complexity and processing overhead increase

Engineering Contradiction:
Improvedata integrityVSAvoiderror correction system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error correction system dynamically adjusts coding rates and activates additional error correction sub-modules based on real-time error rate monitoring and sector age. This dynamic adaptation allows the system to provide high data integrity when errors occur while avoiding the constant complexity overhead of always-maximum error correction, balancing reliability with manageable device complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different coding rates and error correction capabilities are applied to different sectors based on their individual error rates and age characteristics. Rather than uniformly increasing error correction resources across the entire memory, the system applies enhanced correction only to sectors that need it, improving data integrity for at-risk data while minimizing overall system complexity.

Inventive Principle:
Principle #3Local quality

3Reliability

If dynamic adaptation of coding rates is implemented based on age and error rates, then error correction effectiveness improves, but processing time and computational overhead increase

Engineering Contradiction:
Improveerror correction effectivenessVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs error rate monitoring and coding rate adaptation in advance during write operations and idle periods, preparing the optimal error correction configuration before read operations are needed. This preliminary action ensures that when data needs to be read or written, the appropriate error correction is already in place, improving error correction effectiveness without adding significant processing time during critical data operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8966347B2Forward error correction with parallel error detection for flash memories
Publication Date: 2015.02.24 VIASAT INC
  • US8966347B2 patent drawing
  • US8966347B2 patent drawing
  • US8966347B2 patent drawing

AI summary

Methods, systems, and devices are described for forward error correction for flash memory. Encoded data from flash memory may be used to generate a number of data streams. At each of a number of error detection sub-modules operating in parallel, a different one of the data streams is processed. Each error detection sub-module may detect whether a portion of the respective received stream contains an error, and forward the portion to an error correction module. The error correction module, physically separate from the error detection sub-modules, may correct the forwarded portions of the respective received streams containing an error. The age and error rate associated with the flash memory may be monitored, and a coding rate or other aspects may be dynamically adapted to account for these factors.