Flash Memory Fin Structure Isotropic Etching for Leakage Prevention
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Solution Overview
Problem
Conventional methods for fabricating flash memory devices often result in current leakage between floating gates due to incomplete removal of dielectric layers, leading to electrical connectivity issues between floating gates.
Innovation Solution
A method involving the formation of fin structures with a floating gate material, oxide layer, and semiconductive layer, followed by conformal dielectric layer coverage, and subsequent isotropic etching steps to expose and pattern the floating gate material, ensuring proper isolation and preventing electrical connections between floating gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used, then the manufacturing process is simple, but current leakage occurs between floating gates
Solution Approach 1:
The fabrication process is divided into multiple sequential steps: forming dielectric layers at different heights, performing first isotropic etching to remove exposed dielectric, performing second isotropic etching to further expose floating gate material, and finally patterning. This segmentation ensures complete removal of dielectric between floating gates while maintaining manufacturing control
Solution Approach 2:
Dielectric layers are formed in advance at different heights before etching operations. The preliminary formation of these structured dielectric layers with different heights enables subsequent isotropic etching to selectively remove material and expose floating gate material for proper patterning, ensuring electrical isolation is achieved through pre-planned structural preparation
2Reliability
If dielectric layer removal is incomplete, then manufacturing is easier, but electrical connectivity issues occur between floating gates
Solution Approach 1:
The etching process uses isotropic etching which removes material uniformly in all directions, dynamically adapting to the three-dimensional structure formed by dielectric layers of different heights. This dynamic etching approach ensures complete removal of exposed dielectric material regardless of the complex geometry, achieving thorough exposure of floating gate material for proper patterning
Solution Approach 2:
The invention introduces vertical dimensionality by forming dielectric layers at different heights. This multi-level dielectric structure enables the isotropic etching process to effectively remove dielectric material from all exposed surfaces, ensuring complete clearance between floating gates in three-dimensional space rather than relying on simple planar removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents current leakage by ensuring complete removal of dielectric layers and proper patterning of floating gates, enhancing the electrical isolation between them and improving the reliability of flash memory devices.
Implementation Method 1
at least one first isotropic etching step is performed to remove the exposed dielectric layer until the exposed dielectric layer is removed entirely to expose the floating gate material underneath the exposed dielectric layer
Data Source
AI summary
A method of fabricating a flash memory includes providing a fin structure. The fin structure includes a floating gate material, an oxide layer and a semiconductive layer. An insulating layer is disposed at two sides of the fin structure. Then, a dielectric layer conformally covers the floating gate material and insulating layer. Later, a patterned first mask layer, a patterned second mask layer, and a control gate are stacked on the dielectric layer from bottom to top. The control gate crosses at least one fin structure. Next, at least one isotropic etching step is performed to entirely remove the exposed dielectric layer.