Single Flash Memory Firmware Update via Address Remapping

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Solution Overview

Problem

Conventional firmware-over-the-air (FOTA) update methods require multiple flash memory devices, leading to increased costs and performance limitations due to capacitive loading on the bus, and compatibility issues with controllers that lack nonvolatile memory for swap-indicator data.

Innovation Solution

A system that updates firmware using a single memory device by programming a new firmware image within the same device and employing an internal remapping data structure to switch to the new image instantly, eliminating the need for multiple devices and reducing bus capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple flash memory devices are used for firmware updates, then firmware update capability is achieved, but system cost increases and bus performance deteriorates due to capacitive loading

Engineering Contradiction:
Improvefirmware update capabilityVSAvoidnumber of memory devices
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple firmware image storage locations into a single flash memory device by creating multiple virtual address spaces that map to different physical regions within the same device. This allows the system to maintain multiple firmware images (current and new) while using only one physical memory device, thereby reducing system cost and eliminating the capacitive loading issues associated with multiple devices on the bus.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an address space dimension by implementing a mechanism that maps logical addresses to physical addresses through a translation layer. This allows multiple firmware images to coexist in different address ranges within the same physical device, enabling the system to achieve multi-image functionality without requiring multiple physical devices.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple flash memory devices are used for firmware updates, then firmware update capability is achieved, but system cost increases

Engineering Contradiction:
Improvefirmware update capabilityVSAvoidnumber of memory devices
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines the functionality of multiple memory devices into a single device by implementing virtual address spaces that map to different regions within the same physical flash memory. This eliminates the need to purchase and install multiple separate memory devices while maintaining the capability to store and switch between multiple firmware images.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If multiple flash memory devices are connected to the bus, then firmware update capability is achieved, but bus performance decreases due to capacitive loading

Engineering Contradiction:
Improvefirmware update capabilityVSAvoidbus speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

By merging multiple firmware image storages into a single flash memory device, the patent eliminates the need for multiple devices to be connected to the bus simultaneously. This reduces the total capacitive loading on the bus and maintains higher bus speeds, while still providing the capability to store and switch between multiple firmware images through address space mapping.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11537389B2Memory devices, systems, and methods for updating firmware with single memory device
Publication Date: 2022.12.27 INFINEON TECHNOLOGIES LLC
  • US11537389B2 patent drawing
  • US11537389B2 patent drawing
  • US11537389B2 patent drawing

AI summary

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.