Multi-Level Flash Memory Programming with Flag Cell Verification
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Solution Overview
Problem
Multi-level flash memory devices face challenges in precise programming, leading to potential data loss due to interruptions or disconnections, as they require narrower threshold voltage ranges and increased precision, which existing methods struggle to maintain consistently.
Innovation Solution
The method involves using a flag cell and multi-bit storage cells to program threshold voltages within specific ranges, employing Incremental Step Pulse Programming (ISPP) to achieve high precision, and utilizing a flag cell to signal MSB data programming, ensuring accurate data representation across multiple states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level flash memory stores more than one bit per cell by differentiating several levels of charge, then storage capacity increases, but programming precision requirements increase leading to potential data loss
Solution Approach 1:
The patent segments the programming process into multiple discrete steps with verify operations between each step. The threshold voltage programming is divided into incremental stages (e.g., first threshold level, second threshold level, third threshold level), with verification performed after each programming step to ensure precision and prevent data loss.
Solution Approach 2:
The patent performs preliminary verification operations before finalizing the programming state. By verifying the threshold voltage after each programming step and before transitioning to the next level, the system ensures that each charge level is accurately established, preventing programming errors that could lead to data loss.
2Measurement precision
If narrower threshold voltage ranges are used to increase precision, then data storage accuracy improves, but the risk of data loss due to interruptions increases
Solution Approach 1:
The patent performs preliminary verification operations before finalizing each programming state. By verifying the threshold voltage after each programming step and before transitioning to the next level, the system ensures that each charge level is accurately established and stored in a verified state that can withstand interruptions.
Solution Approach 2:
The patent implements a feedback mechanism where the verify operation reads back the programmed threshold voltage to confirm it falls within the expected range. This feedback loop allows the system to detect and correct programming errors before they result in data loss, even in the event of interruptions.
3Measurement precision
If multiple verify voltages are used to read threshold voltage ranges, then read accuracy improves, but the complexity of the reading operation increases
Solution Approach 1:
The patent segments the read operation into multiple discrete verification steps, each using a specific verify voltage corresponding to a threshold voltage range. By organizing the read operation into segmented steps with clear voltage levels, the system achieves high read accuracy while maintaining a structured, manageable process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming precision, reduces the risk of data loss by maintaining accurate threshold voltages and allowing for reliable data storage even in the event of interruptions, ensuring robustness in multi-level flash memory devices.
Implementation Method 1
the floating gate 14 is completely insulated, charge that may be stored within the floating gate is trapped and thus data may persist in the floating gate without the consumption of electricity
Implementation Method 2
NOR flash utilizes a process called hot electron injection to trap charge within the floating gate and relies on quantum tunneling to discharge the floating gate
Implementation Method 3
NOR flash utilizes a process called hot electron injection to trap charge within the floating gate
Implementation Method 4
NAND flash utilizes quantum tunneling both to trap charge and discharge
Data Source
AI summary
A method for programming multi-level non-volatile memory including at least one flag cell and a plurality of multi-bit storage cells. Each storage cell stores data of a least significant bit (LSB) and a most significant bit (MSB). The cells are programmed with LSB data such that programmed storage cells have a threshold voltage greater than VR1. The threshold voltage is modified to have a threshold voltage greater than VR2 for a third or fourth value. The cells are programmed with MSB data for a threshold voltage lower than a VR1 for a first value greater than VR1 and lower than VR2 for a second value, greater than VR2 and lower than VR3 for a third value, and greater than VR3 for a fourth value. VR1 is less than VR2 which is less than VR3. The flag cell is programmed to signal whether MSB data has been programmed.