Flash Memory Flag Cell Program State Detection

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Solution Overview

Problem

Flash memory devices with multi-level cells (MLCs) face challenges in ensuring high reliability during data reading, particularly when abnormal conditions such as power loss occur during programming, leading to incomplete program states and data integrity issues.

Innovation Solution

The method involves using flag cells to indicate the program state of MLCs, employing specific read voltages to determine the completion of programming states for accurate data reading, and optionally fixing data to a set value when incomplete programs are detected, ensuring reliable data output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If MLC programming is performed to increase storage capacity, then data storage density is improved, but data reliability deteriorates due to incomplete program states from power loss

Engineering Contradiction:
Improvedata storage densityVSAvoiddata reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

Flag cells are programmed in advance to record the program state of MLCs before actual data programming occurs. This preliminary action allows the system to track programming progress and detect incomplete programs due to power loss, thereby maintaining data reliability while enabling high-density MLC storage.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple read voltages are used to verify program completion, then data reading accuracy is improved, but operation complexity increases

Engineering Contradiction:
Improvedata reading accuracyVSAvoidoperation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Flag cells serve as intermediary elements that simplify the verification process. Instead of directly checking MLC program completion with multiple read voltages, the system reads the flag cells first to determine program state. This intermediary approach maintains reading accuracy while reducing operational complexity by providing clear guidance on whether verification is needed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If flag cells are programmed to track MLC program state, then data integrity is improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device is segmented into functional components: flag cells for state tracking and MLCs for data storage. This segmentation allows the flag cells to independently record program status without interfering with the high-capacity MLC storage, thereby maintaining data integrity while managing device complexity through functional separation.

Inventive Principle:
Principle #1Segmentation

4Measurement precision

If verification reading is performed before data output, then data accuracy is improved, but operation time increases

Engineering Contradiction:
Improvedata accuracyVSAvoidoperation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The verification process is made dynamic by first reading flag cells to determine program completion status. Only when flag cells indicate incomplete programming does the system perform the time-consuming verification reading of actual data. This dynamic approach maintains data accuracy while minimizing operation time by avoiding unnecessary verification steps.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7782667B2Method of operating a flash memory device
Publication Date: 2010.08.24 SK HYNIX INC
  • US7782667B2 patent drawing
  • US7782667B2 patent drawing
  • US7782667B2 patent drawing

AI summary

A method of operating a flash memory device includes reading a first bit data by employing a first read voltage or a second read voltage higher than the first read voltage according to a program state of a first flag cell. The first flag cell is programmed when the first bit data is programmed into the MLC. A second bit data may be read by employing a third read voltage that is higher than the first read voltage or the second read voltage, or by employing the first read voltage and the third read voltage according to a program state of a second flag cell. The second flag cell is programmed when the second bit data is programmed into the MLC. Alternatively to reading the second bit data, the second bit data is fixed to a set data and the set data is output.