3D Flash Memory Floating Gate Length via IPD2 Flank Removal
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Solution Overview
Problem
In flash memory devices, the presence of thick flank portions of inter-poly dielectric (IPD) layers around the floating gate causes capacitive interference and unwanted charge trapping, degrading performance and limiting the length of the floating gate, which is essential for better channel control and future scaling.
Innovation Solution
The IPD2 layer does not flank the floating gate, allowing for an increased length of the floating gate relative to the control gate, which improves performance by reducing capacitive interference and enabling future scaling by allowing the control and floating gate lengths to be reduced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick flank portions of IPD layers are present around the floating gate, then the IPD layer provides sufficient insulation and structural support, but capacitive interference and charge trapping occur, degrading memory performance
Solution Approach 1:
The patent removes the problematic flank portions of the IPD2 layer that laterally flank the floating gate. By selectively eliminating these specific regions while maintaining the IPD layer structure in other areas, the harmful capacitive interference and charge trapping are eliminated while preserving the necessary insulation and structural support functions in the remaining IPD layer regions.
Solution Approach 2:
The patent applies different structural configurations to different regions of the IPD layer. The IPD2 layer is configured to not flank the floating gate in specific lateral regions where it would cause harm, while maintaining its insulating function in other regions. This local differentiation allows the structure to provide protection where needed while avoiding harmful interactions in critical areas.
2Length of moving object
If thick flank portions of IPD layers are present around the floating gate, then the IPD layer structure is complete and provides structural support, but the floating gate length is limited, preventing better channel control and future scaling
Solution Approach 1:
The patent extracts or removes the flank portions of the IPD2 layer that laterally flank the floating gate. This elimination creates additional space that allows the floating gate length to be increased while maintaining the overall IPD layer structural support function in non-flank regions.
Solution Approach 2:
The patent segments the IPD layer configuration by distinguishing between regions where the IPD2 layer flanks the floating gate and regions where it does not. This segmentation allows the floating gate to extend longer in areas where IPD flanking is removed, while the IPD layer maintains its structural integrity in other areas through the presence of IPD1 and IPD3 layers.
3Productivity
If the IPD2 layer laterally flanks the floating gate, then the manufacturing process is straightforward with continuous layers, but unnecessary IPD material increases device size and reduces scalability
Solution Approach 1:
The patent removes the unnecessary flank portions of the IPD2 layer that would laterally flank the floating gate. This extraction eliminates wasted IPD material while maintaining the continuous layer structure and manufacturing simplicity in the remaining regions, thereby reducing overall device size and improving scalability.
Solution Approach 2:
The patent discards the unnecessary IPD2 flank portions that do not serve a functional purpose. By removing these redundant materials, the device size is reduced and scalability is improved, while the essential IPD layer structures are preserved and optimized for their intended functions.
Data Source
AI summary
An integrated circuit memory cell includes a floating gate, a control gate, and a plurality of inter-poly dielectric (IPD) layers. The IPD layers include an IPD1 layer, an IPD2 layer, and an IPD3 layer, with the IPD2 layer interposed between the IPD1 and IPD3 layers. The IPD2 layer, which may be a nitride, does not flank the floating gate. Thus, no section of the floating gate is laterally between two sections of the IPD2 layer. Also, no section of the IPD2 layer of a first memory cell is between the floating gate of the first memory cell and a floating gate of an immediate adjacent memory cell of the same memory cell string. In some cases, an IPD4 layer is provided between the floating gate and the IPD3 layer. The IPD4 layer is relatively much thinner than layers IPD1-3 and may flank the floating gate, as may the IPD3 layer.