Flash Memory Floating Gate Recesses for Lower Voltage Programming
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Solution Overview
Problem
Conventional flash memory devices face challenges in reducing power consumption while maintaining programming reliability, as they require higher voltages for effective programming, which affects their efficiency and longevity.
Innovation Solution
The introduction of a floating gate with recesses and a blocking layer configuration enhances the coupling ratio between the floating gate and the control gate, allowing for programming at lower voltages by increasing the capacitance of the blocking layer, thereby improving programming reliability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory programming is performed, then programming reliability is maintained, but power consumption increases due to higher voltage requirements
Solution Approach 1:
The patent introduces recesses at specific locations on the floating gate structure to locally enhance the electric field and capacitance coupling. This localized structural modification allows for improved programming reliability at reduced voltages by concentrating the electrical interaction in critical regions rather than requiring uniform high voltage across the entire structure.
Solution Approach 2:
The patent modifies the physical parameters of the floating gate structure by creating recesses that change the capacitance coupling between the control gate and floating gate. This parameter change enables effective programming at lower voltages while maintaining reliability, directly addressing the power consumption issue.
2Reliability
If higher voltages are applied for programming, then programming reliability improves, but power consumption increases
Solution Approach 1:
By creating recesses at specific locations on the floating gate, the patent locally enhances the electric field strength and capacitance coupling efficiency. This allows reliable programming to be achieved at lower voltages by concentrating the electrical interaction in optimized regions, thereby reducing overall power consumption while maintaining programming reliability.
Solution Approach 2:
The structural modification of adding recesses changes the capacitance parameters of the floating gate system. This parameter change enables the system to achieve the same programming reliability at lower voltage levels, directly reducing the power required for programming operations.
3Use of energy by moving object
If the coupling ratio between floating gate and control gate is increased, then programming can be performed at lower voltages, but device complexity increases
Solution Approach 1:
The recesses are introduced at specific strategic locations on the floating gate structure rather than uniformly across the entire structure. This localized approach enhances the coupling ratio effectively while adding minimal structural complexity, allowing lower voltage programming without significantly complicating the device design.
Solution Approach 2:
The patent introduces vertical dimension changes by creating recesses that extend into the floating gate structure. This dimensional modification increases the coupling ratio and capacitance effect without requiring additional lateral components or complex multi-layer structures, thereby achieving lower voltage operation with relatively simple device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables flash memory cells to be programmed at lower voltages, leading to reduced power consumption and enhanced reliability, making the technology more efficient and effective.
Implementation Method 1
increasing the capacitance of the blocking layer, thereby improving programming reliability
Implementation Method 2
Each memory cell may be programmed or electrically charged by injecting electrons into the floating gate from the substrate through the oxide layer
Data Source
AI summary
A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.