Flash Memory Floating Gate Surface Smoothing via Dielectric Buffer
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Solution Overview
Problem
The rough sidewall of the floating gate in flash memory devices often results in voids or seams when the inter-gate dielectric and control gate are filled, leading to reduced reliability and yield due to damage and electrical disturbances.
Innovation Solution
A method involving the formation of a first and second dielectric layer, an isolation structure, and a rapid thermal annealing process to enhance Si—N bonding between the second dielectric layer and the floating gate, followed by etching to expose the isolation structure and protect the floating gate with a remaining dielectric layer, ensuring a smooth surface and preventing voids or seams in the control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating gate sidewall is rough, then the manufacturing process is simpler, but voids or seams are formed in the control gate reducing reliability and yield
Solution Approach 1:
The patent applies preliminary action by forming a protective dielectric layer on the floating gate sidewall before the control gate formation process. This protective layer is deposited conformally to cover the rough sidewall surface, and then planarized to provide a smooth template for subsequent control gate material deposition, preventing void and seam formation while maintaining manufacturing simplicity
Solution Approach 2:
The patent introduces an intermediary protective dielectric layer between the floating gate and the control gate. This intermediary layer serves as a buffer that masks the rough floating gate sidewall surface, allowing the control gate to be formed over a smooth interface, thereby eliminating the direct contact that would cause voids and seams while maintaining process efficiency
2Productivity
If the floating gate sidewall is rough, then material deposition is easier, but voids or seams reduce device yield
Solution Approach 1:
The patent applies preliminary action by forming a protective dielectric layer on the floating gate sidewall before the control gate formation process. This protective layer is deposited conformally to cover the rough sidewall surface, and then planarized to provide a smooth template for subsequent control gate material deposition, preventing void and seam formation while maintaining manufacturing simplicity
Solution Approach 2:
The patent introduces an intermediary protective dielectric layer between the floating gate and the control gate. This intermediary layer serves as a buffer that masks the rough floating gate sidewall surface, allowing the control gate to be formed over a smooth interface, thereby eliminating the direct contact that would cause voids and seams while maintaining process efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and yield of the device by maintaining a smooth floating gate surface, reducing voids and seams in the control gate, and enhancing electrical isolation, thereby stabilizing the memory device operation.
Implementation Method 1
A heat treatment is performed on the second dielectric layer to enhance bonding between the second dielectric layer and the first conductive layer
Implementation Method 2
An etching process is performed to remove a portion of the second dielectric layer so as to expose the top surface of the isolation structure
Data Source
AI summary
A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.