Flash Memory Floating Gate Spacer Design
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Solution Overview
Problem
In flash memory devices, the formation of a stringer in the control gate due to the negative slope of the floating gate reduces the capacitance of the interlayer dielectric film, leading to a lower coupling ratio and reduced program speed, which necessitates increased voltage and higher load on transistors.
Innovation Solution
A method of fabricating a flash memory device that involves forming a pad insulating film and a hard mask film on a semiconductor substrate, creating trenches, forming element isolation films, removing the hard mask and pad insulating film using an isotropic etch process, forming floating gates with tunnel insulating films, removing element isolation films to a predetermined thickness, and forming electrode spacers on the floating gates, followed by the formation of a control gate with an interlayer dielectric film, thereby preventing the formation of a stringer and maintaining capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If anisotropic dry etch is performed without wet-etching the element isolation films, then the stringer formation is prevented, but the element isolation films remain thickly on sidewalls reducing the capacitance of the interlayer dielectric film
Solution Approach 1:
The patent applies preliminary action by performing wet etching of the element isolation films before the anisotropic dry etching of the control gate. This preliminary wet etching step removes the element isolation films from the sidewalls of the floating gate, preventing them from interfering with the subsequent control gate formation and eliminating stringer formation while preserving the capacitance of the interlayer dielectric film.
2Shape
If wet etch method is used to lower the height of element isolation films, then the floating gate negative slope is formed, but the control gate stringer is inevitably formed due to shadowing effect
Solution Approach 1:
The patent applies preliminary action by performing wet etching of the element isolation films before the anisotropic dry etching of the control gate. This preliminary wet etching step removes the element isolation films from the sidewalls of the floating gate, preventing them from interfering with the subsequent control gate formation and eliminating stringer formation while preserving the capacitance of the interlayer dielectric film.
3Speed
If externally applied voltage is increased to compensate for reduced program speed, then the program speed is maintained, but the load on transistors increases
Solution Approach 1:
The patent applies the taking out principle by removing the element isolation films from the sidewalls of the floating gate through wet etching before control gate formation. This extraction eliminates the source of stringer formation and preserves the capacitance of the interlayer dielectric film, thereby maintaining the coupling ratio and program speed without requiring increased voltage, thus reducing the power load on transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method secures the capacitance of the interlayer dielectric film without loss, prevents the formation of a control gate stringer, and enhances program speed by maintaining the coupling ratio, allowing for reliable fabrication of flash memory devices with reduced voltage requirements.
Implementation Method 1
removing the hard mask film and the pad insulating film by means of an isotropic etch process
Implementation Method 2
data can be stored by injecting or extracting electrons into or from the floating gate through application of a proper voltage to a control gate and a substrate
Implementation Method 3
the capacitance of an interlayer dielectric film can be secured without loss while preventing formation of a stringer of a control gate
Data Source
AI summary
A method of fabricating a flash memory device is disclosed wherein, electrode spacers are formed on sides of self-aligned floating gates having a negative slope. Thus, upon etching of a stack gate after an interlayer dielectric film and a control gate are formed, a stringer of a control gate, which is formed by the negative slope of the self-aligned floating gates, can be prevented. Furthermore, because an isotropic etch process is used to remove element isolation films between the floating gates, the element isolation films do not remain on the sides of the floating gates. It is thus possible to prevent loss of the coupling ratio. Accordingly, failure of devices can be reduced and decreasing the program speed can be prevented.