Flash Memory Floating Gate Coupling Ratio via Self-Aligned STI
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Solution Overview
Problem
The existing fabrication methods for EEPROM type flash memory devices face challenges in achieving a large coupling ratio between the floating gate and the control gate due to physical limitations and increased complexity, particularly when forming self-alignment Shallow Trench Isolation (STI) structures, which results in higher costs and potential misalignment issues as design sizes decrease.
Innovation Solution
The method involves forming a tunnel oxide film and a polysilicon film on a semiconductor substrate, followed by oxidizing the STI sidewalls and gap-filling to prevent voids, and then sequentially forming an ONO film and a control gate on the floating gate, allowing for a larger floating gate size and reduced mask usage, thereby enhancing the coupling ratio and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-alignment STI is formed using conventional methods, then alignment precision is improved, but coupling ratio cannot be increased and fabrication complexity increases
Solution Approach 1:
The patent merges the STI formation and floating gate formation into a single integrated process. The polysilicon film is deposited continuously across the substrate before STI etching, so that the floating gate material is already in place when the STI is formed. This eliminates the need for separate floating gate deposition and patterning steps, reducing fabrication complexity while maintaining self-alignment precision.
Solution Approach 2:
The patent applies preliminary action by depositing the polysilicon film for the floating gate before the STI etching process. This ensures that the floating gate material is already positioned and will be automatically aligned with the STI structure when the etch is performed, eliminating the need for subsequent alignment operations and reducing overall process complexity.
2Device complexity
If additional mask is used to form floating gate, then coupling ratio can be increased, but fabrication cost and complexity increase
Solution Approach 1:
The patent combines the floating gate formation with the STI formation process by depositing the polysilicon film before etching. This merging of operations achieves the necessary coupling ratio without requiring an additional photomask, thereby reducing fabrication cost and complexity.
Solution Approach 2:
The polysilicon film serves multiple functions: it acts as the floating gate material and simultaneously provides the structural foundation for self-alignment during STI formation. This multi-functionality eliminates the need for separate masking operations, reducing both cost and complexity while achieving the desired coupling ratio.
3Area of moving object
If design size is reduced, then device integration is improved, but overlay margins become impossible to achieve
Solution Approach 1:
The patent employs self-service through self-alignment, where the floating gate structure automatically aligns with the STI during the etching process. The polysilicon film that forms the floating gate also serves as the reference for alignment, eliminating the need for external overlay margins. This self-aligning mechanism enables continued scaling to smaller device sizes without compromising precision.
4Device complexity
If STI is gap-filled without oxide-oxidization, then process simplicity is improved, but voids are formed in STI
Solution Approach 1:
The patent applies preliminary action by performing oxide-oxidation on the STI sidewalls before the gap-fill process. This preliminary oxidation creates a graded interface that prevents void formation during subsequent material deposition, ensuring STI reliability while maintaining overall process simplicity.
Solution Approach 2:
The patent changes the physical-chemical parameters of the STI sidewalls through oxide-oxidation, transforming the surface properties to be more compatible with the gap-fill material. This parameter change eliminates the void formation issue without requiring complex process modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the coupling ratio between the floating gate and the control gate, reduces fabrication costs, and addresses physical limitations and misalignment issues, while eliminating the need for complex CMP processes and minimizing re-operation, thus improving the efficiency and reliability of the flash memory device.
Implementation Method 1
a tunnel oxide film 110 is formed on an active area of a semiconductor substrate 100
Implementation Method 2
the STI sidewalls are oxidized in an oxide-oxidization method
Data Source
AI summary
A method of fabricating a flash memory which increases a coupling ratio between a floating gate and a control gate in a cell. The method comprises sequentially forming a tunnel oxide film, and polysilicon and first insulation films for a floating gate on an active area of a semiconductor substrate; forming a photoresist as a mask on the first insulation film, and performing an etching process using the photoresist as the mask; forming a hard mask by depositing a second insulation film for prevention of oxidation on the semiconductor substrate; forming an STI by using the hard mask; oxidizing sidewalls of the STI and gap-filling the STI; forming a floating gate by removing the second insulation film remaining as the hard mask; and sequentially forming an ONO film and a control gate on the floating gate.