Flash Memory Programming via Adjacent Floating Voltage
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Solution Overview
Problem
Flash memory devices face inefficiencies in programming time, particularly due to lengthy verification operations, especially when dealing with multilevel cell (MLC) memory cells that require multiple programming loops and verification voltages, leading to increased overall programming time and power consumption.
Innovation Solution
The method involves applying a floating voltage to an adjacent wordline during the verification process, which reduces the influence of parasitic capacitance and shortens the ramp-up time for verifying voltages, thereby reducing verification time and improving programming efficiency without adding complexity or requiring additional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple programming loops with verification voltages are applied to MLC memory cells, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent applies a floating voltage to the adjacent wordline before and during the verification operation. This preliminary action reduces the parasitic capacitance effect in advance, allowing the verification voltage to ramp up faster and complete the verification operation more quickly, thereby reducing overall programming time while maintaining programming accuracy
Solution Approach 2:
The patent changes the voltage parameter of the adjacent wordline from a standard pass voltage to a floating voltage (0V or ground potential). This parameter change eliminates the parasitic capacitance coupling effect, enabling faster verification voltage transitions and reducing verification time without affecting the programming accuracy of the selected memory cells
2Measurement precision
If verification operations are performed with multiple verifying voltages, then verification accuracy is improved, but power consumption increases
Solution Approach 1:
By applying the floating voltage to the adjacent wordline before verification, the patent reduces the capacitive loading that would otherwise require more power to charge and discharge during verification operations. This preliminary action reduces the total power consumption across all verification cycles while maintaining the ability to perform multiple verifying voltage checks for accurate verification
3Reliability
If pass voltages are applied to unselected wordlines during programming, then interference between memory cells is reduced, but verification time increases due to parasitic capacitance
Solution Approach 1:
The patent applies different voltage conditions to different wordlines: the selected wordline receives the program/verify voltage while the adjacent unselected wordline receives a floating voltage (0V). This local differentiation maintains interference protection for non-adjacent wordlines while eliminating parasitic capacitance effects from the adjacent wordline, thereby reducing verification time without sacrificing reliability
Solution Approach 2:
The patent converts the potentially harmful parasitic capacitance effect into a benefit by applying a floating voltage to the adjacent wordline. This transforms the capacitive coupling that would normally slow down verification into a controlled condition where the adjacent wordline acts as a reference ground, enabling faster verification voltage transitions and actually improving verification speed while maintaining cell isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces verification time and enhances programming performance while minimizing power consumption, making it more efficient for programming both 2-bit and 3-bit MLC memory cells.
Implementation Method 1
applying a floating voltage to an adjacent wordline nearest to and programmed after the selected wordline. The influence of the parasitic capacitance between the wordlines can be reduced.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3C
AI summary
A method of programming a flash memory device includes selecting a first wordline of a plurality of wordlines to select a selected wordline, the selected wordline corresponding to a target memory cell and performing a programming loop. The programming loop includes applying a program voltage to the selected wordline and performing a verification to the target memory cell. The verification includes applying a pre-pulse voltage to the selected wordline, applying a plurality of pass voltages to unselected wordlines of the plurality of wordlines, after applying the pre-pulse voltage, applying a series of incremental verifying voltages to the selected wordline, and after applying the pre-pulse voltage, applying a floating voltage to a second wordline of the plurality of wordlines. The second wordline being adjacent to the selected wordline is programmed after the selected wordline.