3D Flash Memory Fringing Effect Charge Storage
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Solution Overview
Problem
Conventional three-dimensional flash memory structures face challenges in forming uniform charge storage regions due to high aspect ratios, leading to non-uniform film deposition and reduced integration capacity, particularly with the ONO structure causing issues in maintaining constant thickness and uniformity of the tunneling insulating layer.
Innovation Solution
The solution involves a flash memory structure with a charge storage layer formed in an intercell insulating layer using a fringing electric field effect, eliminating the need for a blocking insulating layer and allowing for improved uniformity and integration by stacking gate electrodes and intercell insulating layers, with the charge storage layer extending perpendicular to the gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition processes (CVD or ALD) are used to form the ONO structure in high aspect ratio holes, then the charge storage region can be formed, but the film thickness becomes non-uniform (smaller at lower portions, larger toward upper portions)
Solution Approach 1:
The patent extracts and eliminates the blocking insulating layer from the charge storage region structure. By removing this layer, the complex multi-layer ONO structure in high aspect ratio holes is simplified to just the tunneling insulating layer and charge trap layer, which can be formed with better uniformity using deposition processes.
Solution Approach 2:
The charge storage region is segmented into distinct functional layers: the tunneling insulating layer (for charge injection) and the charge trap layer (for charge storage). This segmentation allows each layer to be optimized independently, with the charge trap layer serving both as a storage medium and partially as a blocking layer, thereby achieving the blocking function without requiring a separate thick blocking insulating layer that causes deposition uniformity issues.
2Reliability
If multiple deposition processes are performed to form the ONO structure with heterogeneous films, then the charge storage region can be formed, but the uniformity of heterogeneous films and threshold voltage among cell transistors deteriorates
Solution Approach 1:
The patent merges the blocking insulating layer function into the charge trap layer. The charge trap layer now serves dual purposes: storing charges and providing the blocking function. This consolidation reduces the number of separate deposition processes needed, as the charge trap layer can be formed in a single deposition step rather than requiring separate processes for the blocking insulating layer and charge trap layer.
Solution Approach 2:
The patent changes the material composition and electrical parameters of the charge trap layer to enable it to perform both charge storage and blocking functions. By adjusting the thickness, material composition (e.g., using nitride or oxide-nitride-oxide structures), and trap density of the charge trap layer, it achieves the electrical characteristics of a blocking layer without requiring a separate deposition process for a dedicated blocking insulating layer.
3Productivity
If the ONO structure is used in high aspect ratio holes, then the charge storage function can be achieved, but the integration capacity and string structure formation are limited
Solution Approach 1:
The patent extracts the blocking insulating layer from the high aspect ratio hole structure. By removing this layer, the hole structure becomes simpler and less prone to deposition uniformity issues. The charge trap layer is positioned and configured to provide the necessary blocking function without requiring the complex multi-layer ONO structure that is difficult to form in high aspect ratio holes.
Solution Approach 2:
The patent transitions from a vertical stacking approach (ONO layers stacked vertically in high aspect ratio holes) to a more lateral distribution approach. The charge trap layer is formed with extended lateral dimensions and optimized trap density to provide sufficient blocking function without requiring extreme vertical thickness, thereby reducing the aspect ratio constraints and improving deposition uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of electrical characteristics and increases integration density by eliminating the blocking insulating layer, enabling more efficient program and erase operations and improved string structure formation.
Implementation Method 1
a charge storage layer formed in the intercell insulating layer to store electric charges through a fringing effect of an electric field which is applied from the gate electrode
Data Source
AI summary
Provided are a three-dimensional flash memory using a fringing effect and a method of manufacturing the same. A through hole is formed through a plurality of gate electrodes vertically stacked on a substrate, and the interior of the through hole is filled with a tunneling insulating layer or an active region. Therefore, a charge storage layer is not formed in the through hole, but is formed outside of the through hole. The charge storage layer is formed in an intercell insulating layer filling a gap between the gate electrodes. When a fringing electric field is applied, the electric charges of the active region are trapped in the charge storage layer through the intercell insulating layer.