Flash Memory Fuse Read Verification and Re-Read Mechanism
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Solution Overview
Problem
In NAND-type flash memory, reading setting information from fuse memory during power-on operation is unstable due to fluctuations in power supply voltage, leading to potential errors in setting information written into configuration registers, which can cause incorrect operations and require time-consuming troubleshooting.
Innovation Solution
A semiconductor memory device that includes a power-on operation apparatus to read setting information from a non-volatile memory area, determine if the reading was correct, and re-read the information if necessary, with identification data stored in a register to indicate successful or failed reads, ensuring accurate setting information is used for operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the fuse memory is read during power-on operation before the power supply voltage reaches the operation guarantee voltage, then the power-on operation can be initiated, but the reading becomes unstable and may produce errors due to voltage fluctuations
Solution Approach 1:
The patent applies preliminary action by performing the fuse memory read operation as early as possible during power-on, immediately when the power-on detection level is reached, rather than waiting for the operation guarantee voltage. This early reading initiates the power-on sequence faster, but acknowledges the trade-off of reduced reading stability at lower voltages.
Solution Approach 2:
The patent implements feedback by introducing a verification mechanism that reads feature data from the fuse memory and compares it against expected values. If the feature data verification fails, the system detects the reading error and can trigger a re-read operation, thereby correcting errors caused by unstable voltage conditions during the initial read.
2Reliability
If the fuse memory is read multiple times to ensure correct reading, then the reliability of setting information is improved, but the power-on operation time increases
Solution Approach 1:
The patent applies partial action by performing a minimal verification - reading only the feature data portion of the fuse memory to check for reading correctness, rather than re-reading the entire fuse memory content. This selective verification approach ensures reliability through multiple reads when necessary, while minimizing the time penalty by only re-reading when feature data verification fails.
3Reliability
If feature data verification is performed to detect reading errors, then the reliability of setting information is improved, but the complexity of the power-on operation increases
Solution Approach 1:
The patent extracts the verification function by separating the feature data read and verification steps from the main setting information read operation. The feature data is read and verified independently to detect reading errors, and only if verification fails does the system proceed to re-read operations. This extraction isolates the complexity of error detection into a dedicated verification mechanism rather than complicating the entire read process.
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a memory apparatus and a power-on operation apparatus, and is capable of knowing whether a reading of the setting information which is set during the power-on operation had been completed correctly or not. The flash memory reads the fuse memory when it is detected that the power supply has reached the power-on detection level, and determines whether the reading of the fuse memory had been completed correctly. When not completed correctly, the fuse memory is read again within the maximum read count, and the setting information (which was read from the fuse memory) is written into the CF register. The identification information (that identifies whether the reading of the fuse memory has been completed correctly or not) is stored in the register.