Flash Memory Gate Electrode Edge Processing Withstand Voltage
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Solution Overview
Problem
The existing manufacturing methods for semiconductor devices do not clearly address how to process the edges in the Y direction when cutting the patterned memory gate electrode and control gate electrode portions by etching, which can lead to insufficient withstand voltage between these components.
Innovation Solution
A semiconductor device configuration that includes a semiconductor substrate with a first conductive film and a second conductive film, where the first conductive film has memory gate portions and the second conductive film has control gate portions, both surrounded by insulating spacers and gate insulating films, allowing for increased withstand voltage by maintaining the integrity of the edges and preventing cutting in the middle of coupling portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the material configuring the patterned memory gate electrode portion and that configuring the control gate electrode portion are cut by etching to be spaced apart from each other, then the manufacturing process can be completed, but the edges in the Y direction cannot be properly processed leading to insufficient withstand voltage
Solution Approach 1:
The patent divides the conductive films into separate memory gate portions and control gate portions that are spaced apart in the X direction, while maintaining continuous edges in the Y direction. This segmentation allows each portion to be independently formed and patterned, resolving the manufacturing clarity issue while preserving edge integrity for withstand voltage.
Solution Approach 2:
The patent forms the insulating spacer between the memory gate electrode portion and control gate electrode portion before the etching step. This preliminary action ensures that the edges in the Y direction are protected and properly defined before spacing operations, preventing withstand voltage issues that would arise from improper edge processing.
2Ease of manufacture
If the first conductive film and second conductive film are spaced apart in the X direction, then the memory gate and control gate can be independently formed, but the withstand voltage between them becomes insufficient
Solution Approach 1:
The patent introduces an insulating spacer as an intermediary element positioned between the first conductive film (memory gate) and the second conductive film (control gate). This spacer maintains the necessary spacing for independent formation while providing electrical insulation to ensure sufficient withstand voltage between the spaced-apart conductive films.
Solution Approach 2:
The patent resolves the spacing conflict by utilizing the Z direction (vertical dimension) for the insulating spacer thickness while maintaining X-direction spacing between gate portions. This dimensional approach allows independent gate formation in the X direction while ensuring withstand voltage through the vertical insulating barrier.
3Device complexity
If the edges in the Y direction are not properly processed, then the manufacturing process is simpler, but the current drive capability and data retention characteristics deteriorate
Solution Approach 1:
The patent configures the insulating spacer and gate structures so that the Y-direction edges are naturally defined by the spacer geometry and deposition patterns. The self-aligned nature of the spacer formation process automatically defines clean edges without requiring additional complex processing steps, thus maintaining simplicity while ensuring proper edge quality for current drive and data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the withstand voltage between the conductive films, improves current drive capability, and reduces the cell area of flash memory cells, while maintaining data retention characteristics.
Implementation Method 1
a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate
Data Source
AI summary
A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.