Flash Memory Gate Structure Formation in Scaled CMOS
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Solution Overview
Problem
As CMOS devices are scaled to smaller sizes, existing methods face challenges in forming high-quality gate structures for both NMOS and PMOS transistors, particularly in embedding flash memory, leading to defects and reduced device performance due to the difficulty in forming the second gate material within tight gaps between electrodes.
Innovation Solution
A method involving patterning a first gate material layer and gate insulating film over a substrate, followed by forming and etching a second gate material layer to expose the substrate and form gate structures, which allows for the creation of both control and memory gate electrodes in FMONOS memory cells and MOS transistors, improving device quality and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If existing methods are used to form gate structures for NMOS and PMOS transistors in scaled CMOS devices, then device scaling is achieved, but manufacturing precision deteriorates due to difficulty in forming second gate material within tight gaps between electrodes
Solution Approach 1:
The gate structure formation is divided into multiple sequential steps: first forming a sacrificial gate material layer, then forming the second gate material layer, and finally removing the sacrificial material to create the final gate structure. This segmentation allows each step to be optimized independently, solving the precision problem in tight gaps by breaking down the complex formation process into manageable stages
Solution Approach 2:
The sacrificial gate material layer is formed in advance before the second gate material layer. This preliminary action creates a template structure that guides subsequent material deposition and patterning, ensuring precise gate structure formation even in tightly scaled device geometries where direct formation would be difficult
2Productivity
If device scaling continues to smaller sizes, then productivity increases, but device complexity increases making gate structure formation more difficult
Solution Approach 1:
The multi-layer gate structure methodology serves multiple functions: it forms both control gates and memory gates in FMONOS cells, creates dual-gate structures for enhanced transistor control, and provides a scalable approach applicable to various device geometries. This universal approach simplifies the overall fabrication process despite increased device complexity
Solution Approach 2:
The gate structure employs nested layers where the sacrificial gate material layer is positioned within or adjacent to the second gate material layer. This nesting arrangement allows complex multi-functional gate structures to be built from simpler constituent layers, managing device complexity through hierarchical construction
Data Source
AI summary
A semiconductor device and method for making the semiconductor device comprising a flash memory cell is provided. In accordance with some embodiments, the method includes: patterning a first gate material layer and a gate insulating film over a substrate, the first gate material layer comprising a first gate material, the gate insulating film disposed on the first gate material layer; forming a second gate material layer over the substrate, the gate insulating film, and side walls of the first gate material layer, the second gate material layer comprising a second gate material; etching the second gate material layer to expose the substrate and the gate insulating film and provide a portion of the second gate material layer along each of the side walls of the first gate material layer; and etching the gate insulating film and the first gate material layer so as to form a plurality of gate structures.