Flash Memory Gate Electrode Height Optimization
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Solution Overview
Problem
In the fabrication of flash memory semiconductor devices with split gates, there is a challenge in maintaining reliability and uniformity as the devices scale down, particularly due to issues with current leakage and process charging, which are correlated with the height and uniformity of memory gate electrodes across the memory cell array and shunt regions.
Innovation Solution
The solution involves fabricating flash memory semiconductor devices with distinct heights for the memory gate electrodes in the memory cell array and shunt regions, where the distance between the control gate electrode and the shunt sidewall memory gate electrode is greater than that between the control gate electrode and the cell memory gate electrode, optimizing these distances to prevent current leakage and process charging issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory gate electrode height is increased to improve reliability, then current leakage increases and process charging occurs, but if the height is decreased to prevent these issues, then reliability decreases
Solution Approach 1:
The patent applies local quality by making the memory gate electrode height position-dependent: electrodes in the memory cell array region have a first height while electrodes in the shunt region have a second height. This allows each region to have optimized electrode dimensions suited to its specific functional requirements, preventing current leakage and process charging in the shunt region while maintaining reliable memory operation in the cell array region.
Solution Approach 2:
The patent segments the memory gate electrode structure into distinct height zones corresponding to different functional regions. The control gate is divided such that portions over the memory cell array have different dimensions than portions over the shunt region, allowing independent optimization of each segment's electrical characteristics to avoid harmful effects while maintaining overall device reliability.
2Productivity
If the flash memory device is scaled down to improve integration density, then productivity increases, but manufacturing precision and uniformity across memory cells deteriorate
Solution Approach 1:
By implementing position-dependent memory gate electrode heights, the patent enables local optimization of electrical characteristics across the wafer. This allows different regions to be tuned for their specific functions, compensating for scaling effects and maintaining uniformity in threshold voltage and device performance across all memory cells even as overall device dimensions are reduced for higher integration density.
Data Source
AI summary
The present disclosure provides a method of fabricating a flash memory semiconductor device. In one embodiment, a method of fabricating a resistive memory array includes providing a semiconductor substrate having at least one memory cell array region and at least one shunt region, forming a control gate electrode on the memory cell array region and the shunt region, depositing a dielectric film lamination and a conductive film to cover the control gate electrode and the semiconductor substrate, forming two recesses respectively corresponding to two sides of the control gate electrode on the shunt region, patterning the conductive film to form two sidewall memory gate electrodes and one top memory gate electrode, removing one of the sidewall memory gate electrodes on the memory cell array region, and removing the dielectric film lamination which is exposed from the memory gate electrodes.