Flash Memory Gate Height Reduction via Fluid Photoresist Masking
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Solution Overview
Problem
The increasing aspect ratio of memory cells in non-volatile flash memory devices poses challenges in interlayer dielectric deposition, leading to defects such as through-hole and control gate connections, and poor filling quality, which affects the yield and performance of the devices.
Innovation Solution
A manufacturing method that involves etching the memory control gates using fluid photoresist as a mask to reduce their height by 15%-30%, thereby reducing the aspect ratio and improving the filling quality of the interlayer dielectric between the gates, while ensuring the integration of gate oxide is maintained.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell aspect ratio is increased to maintain functional density, then the number of transistors per chip area increases, but the interlayer dielectric deposition quality deteriorates leading to through-hole defects and poor filling
Solution Approach 1:
The patent segments the gate structure into multiple portions along the channel direction, creating recessed regions between adjacent gate portions. This segmentation allows the ILD layer to be deposited in a stepped configuration, improving filling quality by reducing the aspect ratio of deposition trenches while maintaining the overall high functional density of the memory cell array.
2Manufacturing precision
If the ILD deposition plasma is enhanced to improve filling quality, then the deposition quality improves, but the gate oxide integration fails
Solution Approach 1:
By segmenting the gate into multiple portions with recessed regions between them, the patent creates a stepped ILD deposition structure. This allows milder plasma conditions to be used (preserving gate oxide integrity) while still achieving good filling quality through the geometric configuration of the segmented gates that facilitate progressive ILD layer deposition.
3Productivity
If the memory cell dimensions are reduced to increase production efficiency, then production cost decreases, but the manufacturing process complexity increases and defect susceptibility increases
Solution Approach 1:
The segmented gate structure provides a scalable design that maintains manufacturing feasibility at reduced dimensions. By creating regular patterns of gate portions and recessed regions, the patent enables continued scaling while managing process complexity through geometric simplification of the ILD deposition process.
Solution Approach 2:
The patent introduces vertical dimensionality through the stepped ILD deposition in the recessed regions between gate portions. This dimensional approach allows the structure to accommodate reduced cell dimensions while maintaining adequate ILD filling without proportionally increasing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the filling quality of the interlayer dielectric, reduces the risk of short circuits, and improves the overall performance and yield of non-volatile flash memory devices by maintaining a sufficient safety window for subsequent ion implantation processes.
Implementation Method 1
fluid photoresist filled among the stack gates of the plurality of memory cells as mask
Data Source
AI summary
The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.