Flash Memory Gate Insulating Film Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating flash memory cells with interconnections to first-level polycrystalline silicon films are not compatible with leading logic device processes, causing etching damage and film thickness issues in peripheral transistors, and require additional steps that increase fabrication complexity and cost.
Innovation Solution
A method involving multiple oxidation processes to form gate insulating films of different thicknesses, where the inter-gate insulating film is removed in the region for contact to the gate electrode of the floating gate, using a mask pattern to expose the contact region, eliminating the need for additional photoresist steps and ensuring compatibility with logic device processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to remove the inter-gate insulating film over the first-level polycrystalline silicon film, then the interconnection can be formed in contact with the floating gate, but etching damage occurs to the semiconductor substrate and device isolation film
Solution Approach 1:
The inter-gate insulating film is removed in advance before the contact hole etching step. By performing the removal of the inter-gate insulating film over the first-level polycrystalline silicon film before opening the contact hole, the patent eliminates the need for subsequent etching steps that would damage the substrate and isolation film. This preliminary action resolves the contradiction by achieving interconnection formation capability without causing etching damage.
2Ease of manufacture
If the inter-gate insulating film is removed using additional photoresist steps, then the interconnection can be formed in contact with the floating gate, but the fabrication process complexity increases
Solution Approach 1:
The removal of the inter-gate insulating film is merged with the existing gate electrode patterning process. The same photoresist pattern used for defining the gate electrode also defines the regions where the inter-gate insulating film should be removed. This merging of operations eliminates additional photoresist steps and reduces fabrication process complexity while still enabling interconnection formation to the floating gate.
3Device complexity
If the inter-gate insulating film is not removed, then the fabrication process remains simple, but the interconnection cannot be formed in contact with the first-level polycrystalline silicon film
Solution Approach 1:
The inter-gate insulating film is removed only in the specific regions where interconnections need to contact the first-level polycrystalline silicon film, while remaining intact in other regions. This localized removal is achieved by using the gate electrode photoresist pattern as a mask, ensuring that the insulating film is present where needed for transistor operation but absent where interconnections require contact. This resolves the contradiction by enabling interconnection formation without requiring complete removal or additional process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents etching damage to the semiconductor substrate and device isolation film, maintains transistor characteristics, and simplifies the fabrication process by eliminating the need for extra photoresist steps, thus ensuring compatibility with leading logic device fabrication processes.
Implementation Method 1
In a method for fabricating a semiconductor device, in a multiple oxidation process for forming plural kinds of gate insulating films of different film thicknesses
Data Source
AI summary
The method for fabricating the semiconductor device includes the steps of: forming an insulating film 20, a conductive film 22 and an insulating film 24 over a semiconductor substrate 10 having a first to a third region; removing an insulating film 24, the conductive film 22 and an insulating film 20 formed in the second region and the third region; forming an insulating film 38 in the second region and the third region; removing the insulating film 24 in the first region and the insulating film 38 in the third region; forming an insulating film 44 in the third region; after a conductive film 52 has been formed, patterning the conductive films 22, 52 in the first region to form a gate electrode 58; and patterning the conductive film 52 to form gate electrodes 62 in the second region and the third region while removing the conductive film 52 over the gate electrode 58.