Flash Memory Gate Line Silicide Formation Void Prevention
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Solution Overview
Problem
NAND flash memory devices face challenges in reducing cell-to-cell interference due to narrow distances between word lines, which can lead to seam or void formation in insulating layers, resulting in bridges between cells during metal silicide formation.
Innovation Solution
A method involving the formation of gate lines with a stacked structure of tunnel insulating, floating, and control gate layers on a semiconductor substrate, where a first insulating layer selectively fills gaps between cell gate lines without filling outer spaces of selection gate lines, and a spacer is formed on the outer sides of selection gate lines, followed by a second insulating layer, to prevent interference and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a low k dielectric layer is used between cell gate lines to reduce cell-to-cell interference, then interference is reduced, but seams or voids are generated in the insulating layer due to narrow distances between gate lines
Solution Approach 1:
The patent applies different dielectric materials with different k-values to different spatial locations. Specifically, a first insulating layer with a first k-value is formed in first regions (between cell gate lines), while a second insulating layer with a second k-value is formed in second regions (outer sides of selection gate lines). This local differentiation allows optimization of each region's electrical properties while ensuring complete gap filling where needed.
Solution Approach 2:
The insulating layer is segmented into multiple distinct layers (first insulating layer and second insulating layer) with different material compositions and k-values. This segmentation enables independent optimization of each layer's properties - the first layer addresses interference between cell gate lines while the second layer prevents void formation in outer regions, thereby resolving the contradiction between interference reduction and defect prevention.
2Manufacturing precision
If deposition temperature is reduced to 0°C to 100°C for forming the first insulating layer, then void formation is prevented, but deposition complexity increases
Solution Approach 1:
The patent changes the deposition temperature parameter to a specific range (0°C to 100°C) when forming the first insulating layer. This parameter modification ensures complete gap filling and void prevention in the narrow spaces between cell gate lines. The controlled temperature range optimizes the deposition process for low-k dielectric materials, preventing void formation while maintaining material quality.
Solution Approach 2:
The patent performs preliminary gap filling with the first insulating layer at controlled temperature before forming the second insulating layer. This preliminary action ensures that narrow gaps between cell gate lines are completely filled with the appropriate low-k material, preventing void formation in critical regions before subsequent processing steps are applied to other areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces cell-to-cell interference and prevents seam or void formation, enhancing the packing density and reliability of NAND flash memory devices by using a low-k dielectric layer and specific deposition conditions.
Implementation Method 1
forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up
Implementation Method 2
A metal silicide may be formed on the exposed portion of the polysilicon layer for the control gate
Implementation Method 3
forming a diffusion barrier on the gate lines
Data Source
AI summary
Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.