Two-Step Dry Etching for Flash Memory Gate Oxide Removal
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Solution Overview
Problem
Current methods for fabricating flash memory devices face challenges in completely removing the oxide layer from pre-defined select gate patterns, leading to incomplete removal and potential impacts on the salicide process due to residual oxide on the sidewalls.
Innovation Solution
A two-step dry etching process is employed, where the first etching process uses CF4 to remove part of the oxide layer on top of the gate patterns, and the second etching process uses CF4 and CHF3 at zero bias RF voltage to completely remove the remaining oxide layer from the sidewalls, ensuring full exposure of the polysilicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used to remove the oxide layer, then the process is simple and fast, but the oxide layer on the sidewall is not completely removed which impacts the salicide process
Solution Approach 1:
The single etching process is divided into two sequential etching processes. The first etching process removes the oxide layer from the top surface, while the second etching process removes the oxide layer from the sidewall. This segmentation allows each process to be optimized for its specific target, achieving complete removal without compromising the salicide process.
Solution Approach 2:
The first etching process is performed as a preliminary step to remove the majority of the oxide layer from the top surface before the second etching process. This preliminary action reduces the oxide burden for the subsequent sidewall etching, ensuring complete removal while maintaining process efficiency.
2Productivity
If the oxide layer is not completely removed, then the fabrication process is faster, but the residual oxide on the sidewall interferes with the salicide process
Solution Approach 1:
The fabrication process is segmented into two distinct etching steps with different objectives. The first step prioritizes speed by removing bulk oxide, while the second step prioritizes completeness by removing sidewall oxide. This segmentation resolves the conflict between fabrication speed and salicide process quality.
Solution Approach 2:
Different etching conditions and parameters are applied to different locations of the gate pattern. The first etching process targets the top surface with parameters optimized for rapid removal, while the second etching process targets the sidewall with parameters optimized for complete removal. This local quality approach ensures both speed and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively removes the oxide layer from the select gate patterns, preventing interference with the silicide process and enhancing the fabrication efficiency of flash memory devices by ensuring complete oxide layer removal.
Implementation Method 1
performing a first etching process to remove part of the oxide layer
Implementation Method 2
performing a second etching process to completely remove the remaining oxide layer
Data Source
AI summary
A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.