Flash Memory Gate Electrode PN Junction Depletion Layer
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Solution Overview
Problem
In flash memory devices, the miniaturization of the polysilicon layer used as a floating gate leads to reduced speed and stability due to increased capacitance, and the SONOS flash memory's erase operation efficiency is compromised by backward tunneling charges and the thickness of the blocking oxide layer.
Innovation Solution
A flash memory device with a gate electrode comprising a first conductive layer doped with N impurity and a second conductive layer doped with P impurity is used, where the thickness of the depletion layer between them is increased during an erase operation by applying a negative potential bias, reducing backward tunneling charges and allowing for a thinner blocking insulating layer for improved program speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the blocking oxide layer is increased, then backward tunneling charges are reduced, but program speed is decreased
Solution Approach 1:
The gate electrode is divided into two separate conductive layers: a first conductive layer (N-type) and a second conductive layer (P-type). This segmentation allows independent control of electric field distribution during program and erase operations, enabling the blocking oxide layer to be thinner while maintaining reliability by creating a depletion region that blocks backward tunneling during erase operations.
Solution Approach 2:
The invention dynamically adjusts the electric field distribution by applying different voltages to the first and second conductive layers during program and erase operations. During erase operations, the P-type layer is biased to create a depletion region that dynamically blocks backward tunneling charges, while during program operations, both layers work together to enable efficient charge injection, thus achieving both high speed and reliability.
2Speed
If the thickness of the blocking oxide layer is decreased, then program speed is increased, but backward tunneling charges are increased causing inefficient operation
Solution Approach 1:
The gate electrode is divided into two separate conductive layers: a first conductive layer (N-type) and a second conductive layer (P-type). This segmentation allows independent control of electric field distribution during program and erase operations, enabling the blocking oxide layer to be thinner while maintaining reliability by creating a depletion region that blocks backward tunneling during erase operations.
Solution Approach 2:
The P-type conductive layer acts as an intermediary that creates a depletion region between the control gate and the nitride layer during erase operations. This depletion region serves as a dynamic barrier that prevents backward tunneling charges from reaching the nitride layer, compensating for the reduced physical thickness of the blocking oxide layer and maintaining erase operation efficiency.
3Productivity
If polysilicon layer line width is miniaturized for high integration, then memory density is increased, but capacitance increases reducing speed and stability
Solution Approach 1:
The gate electrode uses a composite structure with N-type and P-type conductive layers, creating a PN junction that generates a depletion region. This composite material approach replaces the traditional single-material floating gate, reducing parasitic capacitance effects while maintaining high integration density, thus improving both speed and stability in miniaturized memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces backward tunneling charges, ensures correct erase operations, and enhances program speed by increasing the Effective Field Height of the blocking insulating layer, while allowing for a thinner blocking insulating layer.
Implementation Method 1
a first conductive layer doped with N impurity and a second conductive layer doped with P impurity are formed over a blocking oxide layer and the thickness of a depletion layer between the first and second conductive layers is increased
Implementation Method 2
backward tunneling charges can be reduced at the time of an erase operation
Data Source
AI summary
A flash memory device includes a tunnel insulating layer formed over a semiconductor substrate, a charge trap layer formed over the tunnel insulating layer and configured to trap electric charges, a blocking insulating layer formed over the charge trap layer, and a gate electrode formed over the blocking insulating layer and including a first conductive layer and a second conductive layer doped with N and P impurities respectively. Further, a method of erasing a flash memory device includes providing a flash memory device including a gate electrode having a first conductive layer and a second conductive layer doped with N and P impurities respectively, and performing an erase operation in a state where a thickness of a depletion layer at an interface of a PN junction comprising the first conductive layer and the second conductive layer is increased due to a negative potential bias applied to the gate electrode.