Flash Memory Gate Structure Protection Against Ion Diffusion
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Solution Overview
Problem
The integration of logic devices into the peripheral region of flash memory systems is hindered by high-temperature processes that affect the diffusion of source and drain regions, making it difficult to control the size of devices in these regions effectively.
Innovation Solution
A method involving the formation of a conformal protective layer on first gate structures to prevent mobile ion interference, followed by a second process that patterns the dielectric and conductive layers to form a second gate structure, allowing for controlled diffusion and reduced device size in the peripheral region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature process is used for flash memory fabrication, then flash memory can be manufactured, but source and drain regions of logic devices experience undesired diffusion making device size control difficult
Solution Approach 1:
The fabrication process is divided into two separate processes: a first high-temperature process for flash memory and a second low-temperature process for logic devices. This segmentation allows each process to operate under optimal temperature conditions, preventing undesired diffusion in logic devices while maintaining flash memory manufacturing requirements
Solution Approach 2:
The first high-temperature process is completed before the second low-temperature process begins. By performing the high-temperature flash memory fabrication first and establishing protective structures (such as protective layers over logic device regions), the subsequent logic device fabrication can proceed under low-temperature conditions that prevent undesired diffusion
2Productivity
If logic devices are integrated into the peripheral region of flash memory, then integration density increases, but device size cannot be effectively controlled due to high-temperature process interference
Solution Approach 1:
Different temperature conditions are applied to different regions of the substrate: the flash memory cell region undergoes high-temperature processing while the peripheral region containing logic devices undergoes low-temperature processing. This local differentiation allows high integration density in the peripheral region without sacrificing device size control
Solution Approach 2:
The substrate is divided into a flash memory cell region and a peripheral region with logic devices, each subjected to appropriate temperature processes. This spatial and temporal segmentation enables both regions to achieve their respective performance goals simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls the diffusion of source and drain regions, enabling the formation of smaller gate lengths and reducing the overall device size in the peripheral region of the integrated circuit.
Implementation Method 1
prevent the mobile ions from diffusing into the first the gate structures
Data Source
AI summary
Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.