Flash Memory Isolation Structure for Controlled Gate Recess
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Solution Overview
Problem
The challenge in forming flash memory structures lies in controlling the recess of the device due to small dimensions, leading to inconsistent positioning of subsequent control gates and potential loss of the floating gate, which affects reliability and yield.
Innovation Solution
A semiconductor structure with a trench and isolation feature, featuring a mask on the sidewall and a dielectric stack layer, is formed using a combination of anisotropic and isotropic etching processes to create controlled openings, reducing damage to the floating gate and improving positioning accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the opening between floating gates is formed by etching process, then the opening can be created, but the depth of the opening is difficult to control due to small dimensions
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps with different depths. First, a shallow opening is etched to a first depth, then a second opening is etched to a greater second depth. This segmentation allows precise control over the depth of each opening independently, solving the problem of depth control in small-dimensional devices.
Solution Approach 2:
The patent performs preliminary actions by forming masks on sidewalls before etching, and by creating the first opening to a controlled depth before proceeding to the second opening. These preliminary steps establish precise depth references and protective structures that enable accurate subsequent etching operations.
2Ease of manufacture
If the etching process is used to form opening, then the opening can be created, but loss of floating gate occurs which decreases reliability and yield
Solution Approach 1:
The patent applies preliminary anti-action by forming protective masks on the sidewalls of the opening before performing the etching process. These masks prevent the etching chemistry from attacking and removing the floating gate material, thereby protecting the floating gate integrity while still allowing the opening to be formed.
Solution Approach 2:
The patent introduces masks as intermediary structures between the etching process and the floating gate. These masks serve as a mediator that allows the etching process to proceed while blocking the harmful effect on the floating gate, enabling opening formation without floating gate loss.
3Length of moving object
If device dimensions are scaled down, then device size is reduced, but control over recess becomes important for device reliability
Solution Approach 1:
The patent segments the recess formation into multiple controlled steps with distinct depth targets. By creating openings at different depths sequentially rather than as a single deep etch, the process maintains precision control over the recess geometry even as overall device dimensions are scaled down.
Solution Approach 2:
The patent uses partial action by creating openings to specific depths that are shallower than a single continuous etch would produce. This partial etching approach, combined with mask protection, prevents over-etching and maintains precise recess control in scaled-down devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and yield of flash memory structures by precisely controlling the formation of control gates and reducing operational interference between adjacent active regions.
Implementation Method 1
using a combination of anisotropic and isotropic etching processes to create controlled openings
Implementation Method 2
using a combination of anisotropic and isotropic etching processes to create controlled openings
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate with a trench between active regions, a tunneling dielectric layer disposed on the substrate, a floating gate layer disposed on the tunneling dielectric layer, and an isolation feature disposed in the trench and on the substrate. The isolation feature has a first opening and a second opening below the first opening. The semiconductor structure further includes a mask disposed on the sidewall of the first opening, and a dielectric stack layer disposed directly above the mask and the second opening.


