Flash Memory Gate Recessing for Lithography Topography Control
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Solution Overview
Problem
In small-scale integrated circuit formation technologies, the topography height difference between flash memory cells and non-memory MOS devices poses challenges for lithography processes, leading to process variations and alignment issues due to the uneven wafer surface.
Innovation Solution
The method involves forming flash memory cells and MOS devices with gates of the same material, where the flash memory cell gate has a thinner top portion than the MOS device gate, and recessing the gate stacks to reduce the topography height difference, allowing for simultaneous formation and leveling of gate surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory cells are formed with multiple layers including floating gate and control gate, then memory functionality is improved, but topography height difference increases making lithography alignment difficult
Solution Approach 1:
The patent applies dimensionality change by forming gates in three-dimensional structures (vertical stacking of floating gate and control gate) while maintaining a planar top surface through recessing. This allows the memory cell to gain vertical dimension for functionality while keeping the horizontal dimension suitable for lithography processes.
Solution Approach 2:
The gate structure is segmented into multiple functional layers (floating gate, control gate, selection gate) that can be formed at different stages and with different materials. This segmentation allows each layer to be optimized for its specific function while the overall structure maintains compatibility with planar processing.
2Adaptability or versatility
If flash memory cells have greater height than MOS devices, then memory cell functionality is achieved, but topography height difference causes process variations
Solution Approach 1:
The invention moves the height difference into the vertical dimension by stacking gates underneath a common planar top surface. The floating gate and control gate are formed at different vertical levels, providing memory functionality while the recessed structure ensures all top surfaces align for consistent processing.
Solution Approach 2:
Different regions of the structure have different qualities: the lower regions contain the multi-layered memory cell gates with varying thicknesses and materials, while the upper region maintains a uniform planar surface. This local differentiation allows functional complexity below while preserving processing uniformity at the surface.
3Manufacturing precision
If topography height difference is reduced by recessing gates, then lithography alignment is improved, but gate thickness varies
Solution Approach 1:
The patent resolves the thickness variation by moving it to the vertical dimension through recessing. The gates are formed with full thickness initially, then selectively recessed to create varying exposed thicknesses that accommodate different device requirements while maintaining a common reference plane for lithography.
Solution Approach 2:
The gates are formed with their full intended thickness before the recessing step. This preliminary formation ensures that each gate achieves its required thickness and material composition, and the subsequent recessing only adjusts the exposed portion without compromising the gate's functional integrity.
Data Source
AI summary
A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.