Flash Memory Gate Structure with Segmented Conductive Patterns
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Solution Overview
Problem
Semiconductor devices, particularly flash memory devices, face challenges in reducing electron back-tunneling and enhancing erase operating characteristics due to the limitations in the design of conductive patterns, which affect the electrical conductivity and signal transmission rates.
Innovation Solution
The semiconductor devices incorporate a first conductive pattern with a smaller width than a second conductive pattern, where the second conductive pattern is thicker and has higher electrical conductivity, and a data storage pattern with a charge trap layer, along with specific dielectric patterns, to facilitate reduced electron back-tunneling and improved erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single width conductive pattern is used, then the manufacturing process is simple, but the electron back-tunneling cannot be effectively reduced and erase operating characteristics are poor
Solution Approach 1:
The gate conductive pattern is segmented into two distinct conductive patterns with different widths. The first conductive pattern has a first width and the second conductive pattern has a second width greater than the first width. This segmentation allows different regions of the gate to serve different functions: the narrower first conductive pattern reduces electron back-tunneling, while the wider second conductive pattern maintains good electrical conductivity and signal transmission.
Solution Approach 2:
Different widths are assigned to different parts of the gate conductive pattern to optimize local functions. The first conductive pattern with smaller width is positioned to primarily reduce electron back-tunneling, while the second conductive pattern with larger width is positioned to provide low resistance electrical connection. This local quality differentiation resolves the contradiction between reducing back-tunneling and maintaining conductivity.
2Reliability
If the conductive pattern width is reduced to reduce electron back-tunneling, then erase operating characteristics improve, but electrical conductivity and signal transmission rates decrease
Solution Approach 1:
The gate is divided into two conductive patterns with different widths positioned at different locations. The first conductive pattern with smaller width is optimized for reducing electron back-tunneling, while the second conductive pattern with larger width is optimized for providing low resistance electrical connection and high signal transmission rate. This segmentation allows both contradictory requirements to be satisfied in different regions.
Solution Approach 2:
The two conductive patterns with different widths are merged together to form a complete gate structure. The first conductive pattern and second conductive pattern are positioned adjacent to each other, with the second conductive pattern extending beyond the first conductive pattern in width. This merging combines the benefits of both narrow and wide conductive patterns into a single functional gate structure.
Data Source
AI summary
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first dielectric pattern, a data storage pattern and a second dielectric pattern, which are sequentially stacked on a semiconductor substrate. A first conductive pattern is provided on the second dielectric pattern. A second conductive pattern having a greater width than the first conductive pattern is provided on the first conductive pattern.