Flash Memory Cell Gate Sharing for Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory cell manufacturing methods struggle to achieve high integration density and memory capacity while maintaining reliability, especially as semiconductor devices scale down to deep sub-micron feature sizes.
Innovation Solution
The method involves forming a floating gate on both sides of a control gate, with an oxide-nitride-oxide spacer in between, allowing two adjacent memory bit cells to share a control gate, and integrating this process with conventional logic processes to enhance memory capacity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional flash memory cell manufacturing methods are used, then manufacturing process is simple, but integration density and memory capacity are limited
Solution Approach 1:
The patent segments the control gate function by allowing two adjacent memory bit cells to share a single control gate. This segmentation approach increases integration density by reducing the number of control gates needed while maintaining proper memory cell functionality through the shared gate structure.
Solution Approach 2:
The patent merges the control gate function across adjacent memory bit cells, where one control gate serves multiple memory cells. This merging strategy reduces overall device complexity and increases integration density by eliminating redundant control gate structures.
2Length of moving object
If memory cells are scaled down to deep sub-micron feature sizes, then device size is reduced, but reliability deteriorates
Solution Approach 1:
The patent transitions from a conventional planar memory cell structure to a three-dimensional stacked gate structure. By adding the vertical dimension with multiple gate layers (first gate, second gate, and control gate), the design achieves deep sub-micron scaling while maintaining reliability through enhanced charge storage and control mechanisms.
Solution Approach 2:
The patent implements a nested gate structure where the first gate and second gate are positioned on opposite sides of the control gate, forming a stacked configuration. This nesting arrangement allows compact deep sub-micron scaling while preserving memory cell reliability through multiple gating layers that work together.
3Quantity of substance
If higher integration density is achieved, then memory capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent creates a universal control gate structure that serves multiple adjacent memory bit cells simultaneously. This multi-functional design increases memory capacity and integration density while reducing manufacturing precision requirements, as the shared control gate can be aligned once to serve multiple cells rather than requiring individual alignment for each cell.
Data Source
AI summary
A method of manufacturing a flash memory cell includes providing a substrate having a first dielectric layer formed thereon, forming a control gate on the first dielectric layer, forming an oxide-nitride-oxide (ONO) spacer on sidewalls of the control gate, forming a second dielectric layer on the substrate at two sides of the ONO spacer, and forming a floating gate at outer sides of the ONO spacer on the second dielectric layer, respectively.