Flash Memory Gate Stack Spacer Fringe Field Inversion
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Solution Overview
Problem
Conventional flash memory device fabrication techniques face challenges in scaling down array dimensions due to short channel effects and damage to the charge trapping layer, limiting the reduction of device dimensions and affecting data retention and gate-to-substrate breakdown voltage.
Innovation Solution
A method involving the formation of gate stacks with a charge trapping layer and control gates, where cell spacers are used to create a fringe field that inverts the silicon substrate during a READ operation, eliminating the need for source/drain regions between gate stacks, thereby reducing short channel effects and minimizing damage to the charge trapping layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication techniques are used to scale down array dimensions, then device density increases, but short channel effects worsen and charge trapping layer damage increases
Solution Approach 1:
The invention segments the channel region by introducing cell spacers that physically divide the continuous channel into isolated sections between gate stacks. This segmentation prevents short channel effects by electrically isolating adjacent memory cells, allowing each cell to be independently controlled without interference from neighboring cells, thus enabling further scaling while maintaining reliability
Solution Approach 2:
The cell spacer acts as an intermediary structure between adjacent gate stacks and charge trapping layers. By positioning the cell spacer in the substrate between gate stacks, it serves as a protective barrier that prevents direct interaction and potential damage between the control gates and the charge trapping layer, thereby preserving data retention characteristics while enabling denser device configurations
2Ease of operation
If source/drain regions are formed between gate stacks, then conventional device operation is achieved, but short channel effects increase and manufacturing complexity increases
Solution Approach 1:
The invention inverts the conventional approach by eliminating source/drain regions between gate stacks and instead using the cell spacer itself to define the active regions. Rather than forming source/drain regions to enable operation, the patent uses the absence of these regions combined with cell spacer-defined fringing fields to achieve device operation, thereby simplifying the structure and reducing short channel effects while maintaining functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the scaling of flash memory devices while reducing or eliminating short channel effects and minimizing damage to the charge trapping layer, improving data retention and gate-to-substrate breakdown voltage.
Implementation Method 1
a fringing field is created between the control gate of the selected gate stack and the silicon substrate and is sufficient to invert a portion of the silicon substrate between the selected gate stack and an adjacent gate stack
Data Source
AI summary
Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.