Flash Memory Gate Structure Stabilization via Selective Charge Layer Removal
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Solution Overview
Problem
The existing manufacturing methods for flash memory face challenges in stabilizing the operation of select gate transistors and increasing processing difficulty due to differences in gate structures and levels between memory cells and select gate transistors, particularly when using MONOS memory cells, which can lead to variations in threshold voltages and require additional processing steps.
Innovation Solution
The solution involves a gate structure where the select gate transistor lacks a charge storage layer, with an intermediate insulating film sandwiched between the gate insulating film and the gate electrode, and a manufacturing method that forms a charge storage layer and block insulating film on the memory cell area while removing the charge storage layer from the select gate area to align the gate structures and reduce processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells and select gate transistors are formed with the same gate structure including charge storage layer, then manufacturing steps can be reduced, but threshold voltage variations occur in select gate transistors causing operational problems
Solution Approach 1:
The patent applies local quality by providing different gate structures in different regions: memory cell regions have charge storage layers for data storage, while select gate transistor regions have only block insulating films without charge storage layers. This regional differentiation allows each structure to be optimized for its specific function, preventing threshold voltage variations in select gates while maintaining manufacturing efficiency through simultaneous formation.
Solution Approach 2:
The gate structure is segmented into functional components: gate insulating film, charge storage layer (present only in memory cells), block insulating film, and gate electrode. By selectively removing the charge storage layer from select gate transistor regions after simultaneous formation, the patent segments the uniform gate structure into functionally differentiated regions, solving the threshold voltage problem while maintaining process efficiency.
2Reliability
If different manufacturing steps are used to form memory cells and select gate transistors with different gate structures, then transistor operation stability is improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent applies preliminary action by forming a uniform gate structure including charge storage layers across both memory cell and select gate transistor regions simultaneously, then selectively removing the charge storage layer from select gate regions in a subsequent step. This approach avoids the complexity of forming different structures from the beginning while achieving the desired functional differentiation.
Solution Approach 2:
The patent extracts the charge storage layer from select gate transistor regions after simultaneous formation of uniform gate structures. By removing only the unnecessary charge storage layer material from select gate areas (while retaining it in memory cell areas), the patent achieves structural differentiation without requiring completely separate manufacturing processes, thus reducing overall complexity.
3Adaptability or versatility
If memory cells have charge storage layer and block insulating film while select gate transistors have neither, then functional requirements are met, but difference in level occurs between gate electrodes increasing processing difficulty
Solution Approach 1:
The patent applies equipotentiality by ensuring that the upper surfaces of the gate structures in both memory cell and select gate transistor regions are at the same level. This is achieved by providing a block insulating film in both regions and selectively removing charge storage layers, then planarizing the surface. The equipotential surfaces eliminate processing difficulties associated with level differences while maintaining functional differentiation through the presence or absence of charge storage layers.
Data Source
AI summary
A nonvolatile semiconductor memory of an aspect of the invention includes memory cells in the memory cell forming area, and select gate transistors in the select gate forming area. Each memory cell has two first diffusion layers formed in a semiconductor substrate, a first gate insulating film formed on the semiconductor substrate, a charge storage layer formed on the first gate insulating film, a first intermediate insulating film formed on the charge storage layer and a first gate electrode formed on the first intermediate insulating film. Each select gate transistor has two second diffusion layers formed in the semiconductor substrate, a second gate insulating film formed on the semiconductor substrate, a second intermediate insulating film formed in direct contact with the second gate insulating film and having the same structure as the first intermediate insulating film, and a second gate electrode formed on the second intermediate insulating film.