3D Flash Memory Gate Structure for Faster Program-Erase Cycles
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Solution Overview
Problem
Conventional flash memory cells with lower coupling ratios experience slower programming and erasing times due to resistance associated with the polysilicon control gate electrode, limiting their performance.
Innovation Solution
The introduction of a shorter control gate electrode and additional electrical contacts to the gate dielectric layer for programming and erasing, eliminating the resistance associated with the polysilicon control gate electrode, thereby increasing the coupling ratio and enhancing programming and erasing speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional flash memory cell structure with polysilicon control gate electrode is used, then the device structure is simple and easy to manufacture, but the resistance associated with the polysilicon control gate electrode results in slower programming and erasing times
Solution Approach 1:
The patent extracts the problematic polysilicon control gate electrode resistance from the conventional flash memory structure by introducing a dual-gate configuration with separate control mechanisms. The first control gate electrode and second control gate electrode are electrically isolated, allowing one gate to be used for programming while the other handles erasing, thereby eliminating the resistance bottleneck of a single polysilicon gate.
Solution Approach 2:
The control gate function is segmented into two separate control gate electrodes (first control gate electrode and second control gate electrode) that are electrically isolated from each other. This segmentation allows independent control of programming and erasing operations, with each gate optimized for its specific function, thereby improving overall speed without compromising structural simplicity.
2Productivity
If the control gate electrode length is reduced to increase coupling ratio, then programming and erasing speeds improve, but the control gate coverage and electrical connection area are reduced
Solution Approach 1:
The patent transitions from a single-dimensional control gate structure to a two-dimensional dual-gate configuration. By stacking or positioning the first control gate electrode and second control gate electrode in different spatial arrangements, the effective control area is increased without extending the lateral footprint, thereby maintaining high coupling ratio while providing sufficient coverage.
Solution Approach 2:
The nested doll principle is applied by positioning one control gate electrode structure within or adjacent to the other, creating a compact three-dimensional arrangement. This nesting allows both control gates to occupy minimal space while maintaining their individual functionality and electrical isolation, effectively increasing coupling ratio without sacrificing coverage area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in faster programming and erasing of flash memory devices by increasing the coupling ratio, thus improving overall performance.
Implementation Method 1
a first tunnel dielectric layer located between the semiconductor substrate and the floating gate electrode
Implementation Method 2
charge accumulation in the floating gate. The charge accumulation in the floating gate may result in induced various capacitances
Implementation Method 3
To program flash memory, a voltage may be applied to the control gate resulting in charge accumulation in the floating gate
Data Source
AI summary
A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.