Flash Memory Gate Dielectric Layout for Lower GIDL Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in reducing gate-induced drain leakage (GIDL) current and power consumption in flash memory devices, particularly due to limitations in gate dielectric thickness and structure.
Innovation Solution
The method involves forming a thicker gate dielectric structure with silicon oxide at the edge of the polycrystalline silicon select gate through thermal oxidation, which reduces GIDL current and gate-drain overlap capacitance, thereby improving high-frequency performance and lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a thinner gate dielectric structure is used, then device scaling and integration density are improved, but gate-induced drain leakage (GIDL) current increases and power consumption increases
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate dielectric structure where the dielectric thickness varies spatially. Specifically, a thicker dielectric layer is formed at the gate edge region compared to the gate center region. This local variation in dielectric thickness allows the gate edge to have higher breakdown strength and lower GIDL current, while the gate center maintains thin dielectric for high integration density and device performance.
2Loss of energy
If a thicker gate dielectric structure is used, then GIDL current and power consumption are reduced, but integration density and device scaling are limited
Solution Approach 1:
The patent segments the gate dielectric structure into distinct regions with different thicknesses. The gate dielectric is divided into a gate edge region with thicker dielectric and a gate center region with thinner dielectric. This segmentation allows each region to be optimized independently: the thick edge region reduces GIDL and power consumption, while the thin center region enables high integration density and device scaling.
3Ease of manufacture
If uniform gate dielectric thickness is used, then manufacturing simplicity is maintained, but GIDL current cannot be effectively reduced
Solution Approach 1:
The patent employs preliminary action by forming a thickness variation profile in the gate dielectric layer before subsequent processing steps. The thicker dielectric at the gate edge is created in advance through controlled deposition or oxidation processes, ensuring that the GIDL-reducing structure is already in place before device assembly and operation. This preliminary structuring enables effective GIDL reduction without complicating the overall manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively attenuates GIDL current and reduces power consumption in semiconductor devices by creating a thicker gate dielectric structure that enhances the performance of flash memory devices.
Implementation Method 1
forming a thicker gate dielectric structure with silicon oxide at the edge of the polycrystalline silicon select gate through thermal oxidation
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.