Flash Memory Hierarchical Address Tables for Write Amplification
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Solution Overview
Problem
Existing flash memory management techniques face issues with 'write amplification factor' (WAF) and lack of robustness against voltage failures, especially in large flash memories, as they require large volatile memory and do not effectively manage memory blocks or reuse memory pages.
Innovation Solution
A flash memory system with hierarchically organized address tables that allow partial memory page addressing, eliminating the need for large volatile memory by storing address tables in flash memory and using a logbook for reconstruction after voltage failures, and dividing memory blocks into static, write, block management, and logbook areas for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large volatile memory is used for address assignment tables to enable direct memory page addressing, then address assignment precision is improved, but device complexity and cost increase due to requirements for large capacitors or batteries for voltage failure protection
Solution Approach 1:
The patent uses small, inexpensive capacitors for voltage failure protection instead of large batteries or complex protection circuits. The capacitors are intentionally designed with limited capacity (short-living) to only maintain address assignment tables during brief power failures, after which the system reconstructs the tables from the logbook. This approach trades the protection duration for simplicity and cost-effectiveness.
Solution Approach 2:
The system implements self-service by automatically reconstructing address assignment tables from the logbook after a voltage failure. Instead of relying on expensive external protection mechanisms, the flash memory system uses its own logbook structure to restore the address mapping information, eliminating the need for large batteries or complex protection circuits.
2Device complexity
If logical block addresses are assigned to physical block addresses, then device complexity is reduced with smaller management tables, but write amplification factor increases because entire physical blocks must be rewritten when small data areas are overwritten
Solution Approach 1:
The patent segments the flash memory into multiple zones (first zone for new data, second zone for updated data, third zone for valid data) and segments the address assignment tables into multiple levels. This segmentation allows selective rewriting of only the necessary zones and table levels, preventing the need to rewrite entire physical blocks when small data areas are overwritten, thus reducing write amplification while maintaining manageable table sizes.
Solution Approach 2:
The patent introduces a hierarchical dimension to address assignment by organizing tables into multiple levels (first level with coarse granularity, second level with fine granularity). This multi-dimensional structure allows the system to manage address mappings efficiently without requiring large flat tables, while enabling selective updates that reduce write amplification by only modifying the necessary portions of the hierarchy.
3Device complexity
If memory blocks are not effectively managed with wear class considerations, then device complexity is reduced, but reliability decreases due to inability to reuse memory blocks and lack of robustness against voltage failures
Solution Approach 1:
The patent implements preliminary action by maintaining a logbook that continuously records address assignment information before voltage failures can occur. This logbook is updated in advance and organized into zones that can be quickly reconstructed. When a voltage failure happens, the system uses the pre-recorded logbook entries to restore the address tables, ensuring reliability without requiring complex real-time protection mechanisms.
Solution Approach 2:
The patent manages memory block reliability by dynamically changing the wear class parameters of memory blocks based on their usage history and error characteristics. The system monitors and adjusts block parameters (such as program/erase cycle counts and error rates) to identify and retire worn blocks, replacing them with fresh blocks from the allocation pool. This parameter-based management extends memory lifespan and improves reliability without requiring overly complex management structures.
Data Source
AI summary
A flash memory for a host system has a multiplicity of memory blocks. The memory blocks are subdivided into memory pages which can be written to and each memory page are also subdivided into partial pages and each partial page having a physical partial page address which is assigned a logical partial page address which can be addressed. The physical partial page addresses assigned to the logical partial page addresses are able to be determined using hierarchically organized structures of address tables for converting logical partial page addresses into physical partial page addresses. The multiplicity of memory blocks of the flash memory are divided into areas which comprise at least one static area of memory blocks which have been written to, a write area to which new and changed useful data are written, a block management area which stores management data for the memory blocks, and a logbook area.