Flash Memory Management via Hierarchical Segmentation
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Solution Overview
Problem
Conventional methods for managing flash memory either require excessive memory for efficient data access or compromise data access efficiency for reduced memory consumption, with existing solutions like the NFTL method experiencing poor performance due to long linked lists during read and write operations.
Innovation Solution
The system configures flash memory using a hierarchy of data access control units including physical erase units, segments, frames, pages, virtual erase units, areas, and clusters, with corresponding tables to manage memory consumption and access efficiency by defining relationships among these units and processing data access through an erase unit table, cluster table, and free segment table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large-size lookup table is used to record LBA to physical address mapping, then data access efficiency is improved, but memory consumption increases significantly
Solution Approach 1:
The patent segments the flash memory into multiple data access basic control units (physical erase units, segments, frames, pages, virtual erase units, areas, clusters) and divides the mapping function into multiple smaller lookup tables (erase unit table, cluster table, free segment table). This segmentation reduces the size of individual lookup tables while maintaining efficient access through hierarchical navigation.
Solution Approach 2:
The patent introduces a hierarchical mapping structure that adds dimensional layers to the address translation process. Instead of a single flat lookup table, the system uses multiple levels of mapping (LBA to cluster, cluster to virtual erase unit, virtual erase unit to physical erase unit), transforming the problem from a two-dimensional lookup into a multi-dimensional hierarchical access structure.
2Quantity of substance
If a lookup table recording only logical erase unit to physical erase unit mapping is used, then memory consumption is reduced, but data access efficiency deteriorates due to required data copying and erasing
Solution Approach 1:
The patent further segments the logical erase unit by introducing virtual erase units and data access basic control units between the logical and physical layers. This additional segmentation allows for more granular control and eliminates the need to copy entire erase units, as operations can be performed on smaller, more manageable units.
Solution Approach 2:
The patent introduces virtual erase units as an intermediary layer between logical erase units and physical erase units. This intermediary structure enables efficient data access by providing a buffer layer that eliminates the need for direct copying and erasing of entire physical erase units, thereby improving access speed while maintaining reduced memory consumption.
3Quantity of substance
If the NFTL method with linked lists is used for mapping, then memory consumption is reduced, but data access efficiency becomes poor due to sequential search requirements
Solution Approach 1:
The patent replaces the linked list structure with a segmented hierarchical structure using multiple lookup tables. Each level of the hierarchy provides direct indexing capabilities, eliminating the need for sequential traversal through linked lists. The segmentation into clusters, virtual erase units, and physical erase units enables efficient direct access at each level.
Solution Approach 2:
The patent performs preliminary organization of data into structured clusters and virtual erase units with pre-computed mapping relationships stored in lookup tables. This preliminary structuring enables direct access without requiring sequential search during actual data operations, significantly improving access efficiency compared to on-the-fly linked list traversal.
Data Source
AI summary
A system and a method for configuration and management of flash memory is provided, including a flash memory, a virtual memory region, and a memory logical block region. The flash memory includes a plurality of physical erase units. Each physical erase unit is configured to include at least a consecutive segment, and each segment is configured to include at least a consecutive frame. Each frame is configured to include at least a consecutive page. Each virtual memory region is configured to include a plurality of areas, and each area is configured to include at least a virtual erase unit. The memory logical block region is configured to include a plurality of clusters, and each cluster includes at least a consecutive memory logical block. By forming correspondence among the physical erase unit, segment, frame, page, virtual erase unit, area, memory logical block and cluster to control the data access to the flash memory, the present invention achieves the reconfiguration and management of memory consumption and access efficiency for the flash memory.