Flash Memory Fabrication Using High-K Metal Gate Process
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Solution Overview
Problem
Conventional integration of flash memory cells fabricated using a polysilicon process with logic circuitry fabricated using a high-k metal gate process in a system-on-chip (SoC) requires additional masks and process steps, increasing manufacturing costs, especially for advanced process technologies like 45.0 nanometer and smaller technologies.
Innovation Solution
A method for fabricating flash memory cells using a high-k metal gate process, which involves forming high-k dielectric and metal gate layers in memory and FET regions of a semiconductor substrate, allowing for concurrent formation of flash memory cells and FETs without requiring additional masks, by patterning and etching these layers in conjunction with forming NFET and PFET gate stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flash memory cells are fabricated using a polysilicon process and logic circuitry is fabricated using a high-k metal gate process, then both types of circuitry can be integrated in an SoC, but additional masks and process steps are required, increasing manufacturing cost
Solution Approach 1:
The patent merges the flash memory fabrication process with the high-k metal gate logic circuitry fabrication process by forming the flash memory floating gate and control gate concurrently with the logic circuitry gates using the same high-k metal gate process steps, eliminating the need for separate polysilicon processing
Solution Approach 2:
The high-k metal gate process is made universal to serve dual purposes: forming gates for logic circuitry (NFET and PFET) and forming the floating gate and control gate for flash memory cells, allowing a single process to accomplish multiple functions that previously required separate specialized processes
2Reliability
If additional masks and process steps are used to integrate flash memory and logic circuitry, then both can be fabricated with their respective processes, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the patterning and etching steps for flash memory gates and logic circuitry gates into unified process steps, where single masks define both flash memory and logic circuitry features simultaneously, and single etching steps form both types of structures
Solution Approach 2:
The patent performs preliminary actions by forming the high-k dielectric and metal gate layers across the entire substrate before any patterning, establishing a universal foundation that enables subsequent concurrent formation of both flash memory and logic circuitry structures without requiring process divergence
Data Source
AI summary
According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric o one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.