Flash Memory Insulating Liners for Short Channel Effect Control
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Solution Overview
Problem
As semiconductor devices shrink, controlling short channel effects and maintaining low resistance source/drain terminals becomes challenging, especially in NOR Flash architectures, leading to performance issues like increased resistance and voltage requirements.
Innovation Solution
The implementation of memory devices with low resistance source/drain junctions and insulating liners surrounding the junctions, using doped amorphous silicon trenches and dielectric charge trapping structures, addresses short channel effects and enables scalable memory arrays with channel lengths less than 200 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk to smaller dimensions, then device density is improved, but short channel effects become difficult to control
Solution Approach 1:
An insulating liner is introduced as an intermediary layer between the source/drain lines and the channel region. This liner acts as a mediator that blocks electric field penetration from the source/drain into the channel, thereby controlling short channel effects while allowing the channel length to be scaled down for higher device density.
2Length of moving object
If doped source/drain lines are made narrower and shallower, then device size is reduced, but resistivity increases
Solution Approach 1:
The insulating liner serves as a barrier that prevents electric field penetration, allowing the source/drain lines to be configured optimally for density without being constrained by the need to maintain low resistance through larger dimensions. The liner enables the use of narrower and shallower doped lines while controlling their electrical characteristics.
Solution Approach 2:
The source/drain lines are doped with high concentration dopants in specific regions to create locally optimized electrical properties. The doping concentration is varied spatially to achieve low resistance where needed while maintaining compatibility with the reduced dimensions and insulating liner structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides high-density flash memory devices with improved performance by reducing off-state current and voltage requirements, effectively managing short channel effects and enabling faster read cycles.
Implementation Method 1
Insulating liners lie between the semiconductor material within the trenches and the semiconductor body... The insulating liners provide isolation between the source/drain lines and the channel regions, thereby reducing off-state current
Implementation Method 2
The trenches are filled with doped amorphous silicon to provide low resistance source/drain lines... The doped amorphous silicon provides good electrical contact and low resistance
Data Source
AI summary
A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.