Flash Memory Controller Interface Double-Edge Clocking

Solution Overview

Problem

Current flash memory devices face challenges in providing an improved interface between the controller and memory array that offers additional bandwidth without increasing power dissipation or surface area, particularly in mitigating intercell interference and enhancing data transmission efficiency.

Innovation Solution

The proposed solution involves an interface that transfers data on one edge of a clock signal and additional information, such as soft data or aggressor cell values, on a second edge, allowing for increased bandwidth for improved intercell interference mitigation without significant power or area increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional bandwidth is provided for carrying additional information about transmitted data, then intercell interference mitigation is improved, but power dissipation and surface area increase

Engineering Contradiction:

Improveintercell interference mitigationVSAvoidpower dissipation

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The interface dynamically utilizes both edges of the clock signal for data transmission, switching between single-edge and double-edge modes. During normal operation, data is transmitted on the rising edge. When additional information needs to be conveyed (such as soft data or aggressor cell values for interference mitigation), the interface activates transmission on both rising and falling edges, providing dynamic adaptability without permanent hardware overhead

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the temporal parameter of the clock signal by utilizing both rising and falling edges for data transmission. This parameter change effectively doubles the available bandwidth during interference mitigation operations without requiring additional physical infrastructure, thereby improving reliability while controlling power dissipation and surface area

Inventive Principle:

Principle #35Parameter changes

2Reliability

If additional bandwidth is provided for carrying additional information about transmitted data, then intercell interference mitigation is improved, but surface area increases

Engineering Contradiction:

Improveintercell interference mitigationVSAvoidsurface area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The interface dynamically utilizes both edges of the clock signal for data transmission, switching between single-edge and double-edge modes. During normal operation, data is transmitted on the rising edge. When additional information needs to be conveyed (such as soft data or aggressor cell values for interference mitigation), the interface activates transmission on both rising and falling edges, providing dynamic adaptability without permanent hardware overhead

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the temporal parameter of the clock signal by utilizing both rising and falling edges for data transmission. This parameter change effectively doubles the available bandwidth during interference mitigation operations without requiring additional physical infrastructure, thereby improving reliability while controlling power dissipation and surface area

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If data is transmitted only on one edge of the clock signal, then power dissipation and surface area are minimized, but bandwidth is insufficient for interference mitigation

Engineering Contradiction:

Improvepower dissipationVSAvoidbandwidth

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The interface dynamically utilizes both edges of the clock signal for data transmission, switching between single-edge and double-edge modes. During normal operation, data is transmitted on the rising edge. When additional information needs to be conveyed (such as soft data or aggressor cell values for interference mitigation), the interface activates transmission on both rising and falling edges, providing dynamic adaptability without permanent hardware overhead

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The invention changes the temporal parameter of the clock signal by utilizing both rising and falling edges for data transmission. This parameter change effectively doubles the available bandwidth during interference mitigation operations without requiring additional physical infrastructure, thereby improving reliability while controlling power dissipation and surface area

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8677056B2Methods and apparatus for interfacing between a flash memory controller and a flash memory array

Publication Date: 2014.03.18 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE LTD

AI summary

Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge.