Flash Memory Allocation Structure for Interleaved Data Writing
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Solution Overview
Problem
Flash memory devices with multi-level cell (MLC) technology face slow data writing rates due to the need to distinguish multiple threshold voltage distributions, leading to inefficient data storage and potential capacity wastage, especially when data amounts do not align with the capacity of physical blocks.
Innovation Solution
A control method and allocation structure for flash memory devices that divide data into subunits and interleave their writing across multiple groups of physical blocks in two memory modules, ensuring an optimal data writing rate and efficient capacity utilization by allowing asymmetric storage and interleaving data across memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC technology is used to store multiple bits per memory cell, then storage capacity is improved, but data writing rate deteriorates
Solution Approach 1:
The patent segments the data writing process into multiple stages with different priorities. Frequently accessed data is written to SLC regions for fast access, while less frequently accessed data is written to MLC regions. This segmentation allows the system to maintain high storage capacity using MLC while ensuring fast data writing rates for critical data in SLC regions.
Solution Approach 2:
The patent applies local quality by creating different storage regions with different characteristics within the same memory system. SLC regions provide fast writing speeds for specific data types, while MLC regions provide high capacity for other data. This local differentiation resolves the contradiction by optimizing each region for its specific purpose rather than requiring uniform performance across the entire system.
2Device complexity
If data is written sequentially into physical blocks, then device complexity is reduced, but memory capacity utilization deteriorates
Solution Approach 1:
The patent segments physical blocks into different types (SLC blocks and MLC blocks) and organizes them into groups that can be managed independently. This segmentation allows the controller to selectively allocate different block types based on data requirements, improving capacity utilization without requiring complex dynamic management of every individual block.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing physical blocks into groups with specific characteristics before data writing begins. Allocation units are pre-configured to span multiple groups, and the controller maintains allocation information that guides future writing operations. This preliminary organization simplifies subsequent data writing operations while maximizing capacity utilization.
3Device complexity
If allocation units are evenly distributed across memory modules, then device complexity is reduced, but data writing rate deteriorates
Solution Approach 1:
The patent introduces asymmetry in the allocation strategy by allowing allocation units to be distributed unevenly across memory modules based on performance requirements. Critical allocation units that require fast writing are concentrated in specific modules or groups, while less critical units are distributed elsewhere. This asymmetric distribution optimizes data writing rate for important data without requiring complex real-time decision-making for every allocation.
Solution Approach 2:
The patent adds another dimension to the allocation problem by considering not just the number of modules but also the hierarchical organization of groups within modules. Allocation units are mapped to specific groups rather than being简单地 distributed across modules, creating a multi-dimensional allocation space that optimizes both performance and simplicity.
Data Source
AI summary
A control method and an allocation structure for a flash memory device are provided herein. The flash memory device has a first memory module and a second memory module. Physical blocks of the first memory module and physical blocks of the second memory module are respectively divided into a plurality of groups, each of which has a plurality of the physical blocks. A first subunit and a second subunit of a first allocation unit are interleavingly written into a first group of the groups of the first memory module and a second group of the groups of the second memory chip respectively. Additionally, a first subunit and a second subunit of a second allocation unit are interleavingly written into a third group of the groups of the first memory module and the second group, respectively.