Flash Memory Interleaving Codeword Portions Planes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices face inefficiencies in programming due to strong coupling between even and odd pages, leading to increased noise and read errors, particularly when programming one row affects information in another row, necessitating improved interleaving schemes to minimize buffering requirements and reduce program disturbs.
Innovation Solution
The proposed solution involves interleaving codeword portions across multiple flash memory planes while violating specific ordering rules, such as the even odd ordering rule, programming type ordering rule, and codeword portions ordering rule, to maintain reliability and reduce noise, using a decoupling sequence that adjusts based on the significance of programming types and noise sensitivity, and employing a logical to physical mapping for optimal programming order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If codeword portions are interleaved across multiple flash memory planes while violating ordering rules, then programming efficiency and throughput are improved, but read reliability may deteriorate due to increased noise and programming disturbances
Solution Approach 1:
The codeword is divided into multiple portions that are interleaved across different flash memory planes. This segmentation allows parallel programming operations on multiple planes simultaneously, improving throughput while the selective violation of ordering rules for only specific portions maintains reliability for the majority of data
Solution Approach 2:
Different ordering rules are applied to different portions of the codeword based on their noise sensitivity. Critical portions maintain strict ordering rules while less sensitive portions can violate ordering rules for improved efficiency. This local differentiation optimizes the balance between reliability and throughput
2Reliability
If strict ordering rules are maintained for all codeword portions, then read reliability is preserved, but programming efficiency deteriorates due to increased buffering requirements and sequential processing
Solution Approach 1:
Instead of applying ordering rules to all codeword portions, the patent applies them only to the extent necessary for maintaining reliability. Critical portions receive full ordering protection while less sensitive portions use relaxed ordering, reducing buffering requirements and improving parallelism
Solution Approach 2:
The patent dynamically adjusts the ordering rule application based on noise sensitivity parameters of different codeword portions. By changing the ordering parameter from strict to relaxed based on the specific portion being programmed, the system optimizes both reliability and efficiency
Data Source
AI summary
A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.