Flash Memory Cell With Inversion Source Drain Regions

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Solution Overview

Problem

Nitride read-only memory flash memory devices face challenges with charge loss, oxide damage, and non-uniform erase speed due to hot hole injection and process variations, leading to poor endurance and increased erase time as technology scales down.

Innovation Solution

A charge-trapping flash memory cell structure with a fin-shaped channel (Si-FIN) layer and inverted source and drain regions, where adjacent poly-gate cells act as passing gates for voltage transfer, enabling efficient programming, erasing, and reading operations without the need for traditional source and drain implantations, and utilizing Fowler-Nordheim tunneling and channel hot electron injection methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If hot hole injection is used to erase nitride read-only memory cells, then erase capability is achieved, but oxide damage occurs leading to charge loss and reduced reliability

Engineering Contradiction:

Improveerase capabilityVSAvoidcharge retention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces a charge trapping dielectric layer as an intermediary between the oxide layer and the channel region. This intermediate layer captures holes during erase operations, preventing them from reaching and damaging the oxide layer, thereby eliminating oxide damage while maintaining erase capability

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful hot holes generated during erase operations into a beneficial function by using them to trap positive charge in the charge trapping dielectric layer. This trapped charge serves as the memory state, transforming the harmful hot holes into useful stored information

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Productivity

If sector erase is performed on nitride read-only memory flash memory device, then erase operation is completed, but non-uniform erase speed occurs due to process variations leading to poor endurance

Engineering Contradiction:

Improveerase speedVSAvoiderase uniformity

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements local quality by creating inversion regions at specific locations (source and drain regions) within each memory cell. These locally modified regions provide controlled electric field distribution during erase operations, ensuring uniform erase characteristics across all cells in the array regardless of process variations

Inventive Principle:

Principle #3Local quality

3Reliability

If traditional source and drain implantation is used in memory cell structure, then proper source and drain regions are formed, but device complexity and manufacturing difficulty increase

Engineering Contradiction:

Improvesource and drain region formationVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by using the channel region itself to form the source and drain regions through inversion. The channel region undergoes local inversion at the source and drain locations during device operation, eliminating the need for separate implantation processes and simplifying the manufacturing workflow

Inventive Principle:

Principle #25Self-service

4Area of moving object

If technology scaling is performed to reduce memory device size, then package density is improved, but charge loss and oxide damage become more severe

Engineering Contradiction:

Improvememory cell sizeVSAvoidcharge retention

Core Design Contradiction:

Area of moving objectVSReliability

Solution Approach 1:

The patent implements nesting by placing the charge trapping dielectric layer within the existing oxide-nitride-oxide stack structure. The charge trapping layer is embedded between the bottom oxide and the nitride layer, creating a nested configuration that maintains charge retention through multiple layered protections while occupying minimal additional space

Inventive Principle:

Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a more compact, scalable, and uniform memory cell structure with improved endurance and reduced erase time, maintaining a narrow threshold voltage window and enhancing package density.

Implementation Method 1

utilizing Fowler-Nordheim tunneling and channel hot electron injection methods

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

adjacent poly-gate cells act as passing gates for voltage transfer

Methodology Applied

Scientific EffectVoltage transfer through inversion regions:

Data Source

PatentUS7471564B2Trapping storage flash memory cell structure with inversion source and drain regions

Publication Date: 2008.12.30 MACRONIX INTERNATIONAL CO LTD

AI summary

Methods of manufacturing a nitride trapping EEPROM flash memory are described where each memory cell uses Si-Fin to form a nitride trapping EEPROM flash cell in which the source region and drain region are undoped. Each adjacent poly-gate to a selected poly-gate in a row of nitride trapping memory cells is used to produce the inversion region that acts as a source region or a drain region for transferring of a required voltage, which conserves the density of a memory cell given that the source region and the drain region for each memory cell are not doped. The flash memory includes a plurality of polysilicon layers intersecting with a plurality of Si-Fin layers.