Flash Memory Cell With Inverted Tunneling for Capacitance Tuning

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Solution Overview

Problem

Conventional flash memory cell fabrication processes struggle to accommodate diverse logic device configurations, such as FinFETS and GAA-FETS, due to the interdependence of tunnel and blocking dielectric dimensions, limiting capacitance ratio tuning and efficiency of program and erase voltages.

Innovation Solution

The implementation of a back end of line (BEOL) flash memory cell with an inverted tunneling configuration allows independent tuning of tunnel dielectric dimensions, decoupling them from blocking dielectric dimensions, thereby optimizing capacitance ratios and reducing the magnitude of program and erase voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional flash memory cell fabrication processes are used, then the manufacturing process is simple, but the tunnel and blocking dielectric dimensions are interdependent, limiting capacitance ratio tuning

Engineering Contradiction:

Improvecapacitance ratio tuningVSAvoidfabrication process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The fabrication process is divided into separate sequential steps: first forming the blocking dielectric with its required dimensions, then subsequently forming the tunnel dielectric with independently controllable dimensions. This segmentation allows the capacitance ratio to be tuned by independently adjusting each dielectric's thickness without being constrained by interdependent dimensions from a single fabrication step.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If the magnitude of program and erase voltages is reduced, then the operational efficiency is improved, but the tunneling of electrons becomes insufficient

Engineering Contradiction:

Improveprogram and erase voltage magnitudeVSAvoidelectron tunneling effectiveness

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The capacitance ratio between the tunnel dielectric and blocking dielectric is optimized by independently controlling their respective dimensions. By adjusting the thickness and area parameters of each dielectric layer, the voltage division ratio changes, allowing sufficient electron tunneling to occur at lower program and erase voltage magnitudes, thus improving operational efficiency while maintaining reliability.

Inventive Principle:

Principle #35Parameter changes

3Power

If the capacitance ratio is optimized, then the voltage efficiency is improved, but the fabrication process becomes more complex

Engineering Contradiction:

Improvevoltage efficiencyVSAvoidfabrication process complexity

Core Design Contradiction:

PowerVSDevice complexity

Solution Approach 1:

The blocking dielectric is formed first with predetermined dimensions optimized for voltage blocking, followed by the formation of the tunnel dielectric with dimensions optimized for electron tunneling and capacitance ratio. This preliminary action approach allows each dielectric to be independently optimized for its specific function, achieving voltage efficiency without requiring complex simultaneous dimensional control.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the operational efficiency of flash memory cells by lowering the write and erase voltages, making them suitable for integration with various logic device configurations and improving the flexibility of flash memory arrays.

Implementation Method 1

Flash memory utilizes the tunneling of electrons into and out of a floating gate in order to change the threshold voltage of the flash memory cell. The tunneling of electrons is induced by applying a program voltage or an erase voltage to the control gate.

Methodology Applied

Scientific EffectQuantum tunneling:

Implementation Method 2

a floating gate extending over the control gate and configured to hold a charge determined by the most recent of the program voltage or erase voltage applied to the flash memory cell, wherein the charge alters a threshold voltage of the flash memory cell

Methodology Applied

Scientific EffectElectrostatic field effect: Electrostatics

Data Source

PatentUS20240363765A1Flash memory cell with tunable tunnel dielectric capacitance

Publication Date: 2024.10.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.