Flash Memory Isolation Structure with Arc-Shaped Top

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Solution Overview

Problem

Conventional flash memory devices often form voids in the polysilicon layer due to small spacing between isolation structures, affecting the quality of the floating gate structure, and attempts to reduce isolation structure size to prevent voids result in reduced isolation effectiveness.

Innovation Solution

A method involving sequential formation of stop and sacrificial layers on a semiconductor substrate, etching to form a groove, filling with insulating dielectric material, and carefully removing layers to form an isolation structure with an arc-shaped top and inclined sidewalls, allowing for improved polysilicon deposition without voids and maintaining isolation effectiveness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the spacing between isolation structures is reduced to increase integration density, then the area occupied by isolation structures increases, but voids form in the polysilicon layer during subsequent deposition

Engineering Contradiction:

Improvearea occupied by isolation structuresVSAvoidquality of polysilicon layer

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The isolation structure top surface is formed with an arc-shaped curvature instead of a flat surface. This curved geometry allows polysilicon to deposit uniformly without forming voids, as the arc shape facilitates complete material coverage during the deposition process while maintaining reduced spacing between isolation structures.

Inventive Principle:

Principle #14Spheroidality (Curvature)

2Manufacturing precision

If the isolation structure size is reduced to prevent voids in polysilicon layer, then voids are prevented, but isolation effectiveness is reduced

Engineering Contradiction:

Improvequality of polysilicon layerVSAvoidisolation effectiveness

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The arc-shaped top surface of the isolation structure enables complete polysilicon coverage without voids while maintaining sufficient isolation dimensions. The curved geometry ensures that polysilicon deposits uniformly across the entire surface, preventing void formation without requiring reduction of the isolation structure size, thus preserving isolation effectiveness.

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The isolation structure has different geometrical characteristics at different locations: the top surface features an arc shape to facilitate polysilicon deposition, while the sidewalls maintain inclined angles for proper structural definition. This localized geometric optimization ensures both void-free polysilicon formation and adequate isolation performance.

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If conventional planar isolation structures are used, then the fabrication process is simple, but voids form in the polysilicon layer affecting floating gate quality

Engineering Contradiction:

Improvefabrication process simplicityVSAvoidquality of floating gate structure

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

Inventive Principle:

Principle #14Spheroidality (Curvature)

Solution Approach 2:

The arc-shaped top surface of the isolation structure is formed in advance before polysilicon deposition. This preliminary geometric preparation ensures that when polysilicon is subsequently deposited, it can uniformly cover the curved surface without forming voids, thereby improving floating gate quality without complicating the overall fabrication process.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9515078B2Semiconductor structure and method for forming the same

Publication Date: 2016.12.06 SEMICON MFG INT (BEIJING) CORP

AI summary

Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary method, a semiconductor substrate is provided. A first stop layer, a first sacrificial layer, a second stop layer, and a second sacrificial layer are formed sequentially on the semiconductor substrate. The second sacrificial layer, the second stop layer, the first sacrificial layer, the first stop layer, and the semiconductor substrate are etched to form a groove, the groove then being filled to form an isolation structure. The second sacrificial layer is removed to expose sidewalls and a top of an exposed portion of the isolation structure. The second stop layer is removed, and the exposed portion of the isolation structure is etched to reduce a width of the top of the exposed portion of the isolation structure. The first sacrificial layer is removed. A floating gate is formed on the first stop layer.