Flash Memory Isolation Layout for Current Crowding Control
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating flash memory devices with high memory array density and efficient charge storage due to the high-voltage operations required for programming and erasing, which can lead to current crowding and non-uniformity in source/drain regions, affecting device performance and yield.
Innovation Solution
A method for fabricating semiconductor devices involves forming recessed regions on a substrate with specific trench profiles and isolation features, using a patterned hard mask to protect the peripheral region during etching, and forming floating gates without planarization to enhance coupling ratios and prevent dishing and erosion, thereby improving thickness uniformity and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-voltage operations are used for programming and erasing flash memory, then storage capability is improved, but current crowding and non-uniformity in source/drain regions occur
Solution Approach 1:
The patent divides the gate structure into control gate and floating gate segments, and divides the source/drain regions into multiple zones with different doping concentrations. This segmentation allows high-voltage programming while distributing current stress across different regions, preventing current crowding and maintaining manufacturing precision.
2Shape
If floating gates are formed with planarization, then surface flatness is improved, but dishing and erosion occur reducing thickness uniformity
Solution Approach 1:
The patent performs preliminary conformal coating of dielectric materials to compensate for anticipated dishing and erosion before floating gate formation. This preliminary action creates a pre-compensated surface that maintains thickness uniformity even after subsequent processing steps cause material removal.
Solution Approach 2:
The patent changes the physical and chemical parameters of dielectric layers by forming multiple layers with different materials and properties (e.g., different etch rates, densities). This parameter changes approach allows the structure to self-compensate for dishing and erosion, maintaining floating gate thickness uniformity without requiring perfect planarization.
3Quantity of substance
If memory array density is increased, then storage capacity is improved, but current crowding in source/drain regions worsens
Solution Approach 1:
The patent applies local quality by creating zones with different doping concentrations in the source/drain regions. High-doping zones are placed in areas experiencing high current density to increase local conductivity and reduce current crowding, while low-doping zones are used in areas where current density is lower. This localized optimization allows higher memory array density without exacerbating current crowding effects.
Data Source
AI summary
An integrated circuit device includes a substrate, a first isolation feature, a memory cell, and a semiconductor device. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. The first isolation feature is in the transition region. The substrate includes a protrusion portion between a first portion and a second portion of the first isolation feature, the second portion is between the first portion and the cell region, and a top surface of the first portion of the first isolation feature has a first part and a second part lower than the first part, and the second part is between the first part and the second portion of the first isolation feature. The memory cell is over the cell region of the substrate. The semiconductor device is over the peripheral region of the substrate.