Flash Memory Isolation Structure Sidewall Mask Protection
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Solution Overview
Problem
In flash memory device manufacturing, the formation of isolation structures with different depths in cell and peri regions leads to gap-fill failure and degradation of gate oxide layers due to the wet etch process, affecting device reliability.
Innovation Solution
A method involving the formation of a sidewall mask with a lip/step in the peri-region isolation trench, using a first gap-fill layer with varying thickness portions to protect the gate dielectric layer during the wet etch process, ensuring the second portion remains intact to prevent gate oxide layer loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a wet etch process is used to remove the deposited insulating layer from the peri region trench, then the insulating layer can be effectively removed, but the gate oxide layers may also be removed degrading device reliability
Solution Approach 1:
The insulating layer is segmented into two distinct layers: a first insulating layer that is selectively removed by wet etch, and a second insulating layer that remains to protect the gate oxide. This segmentation allows differential treatment of insulating materials to achieve both complete removal where needed and protection where required.
Solution Approach 2:
The first insulating layer acts as an intermediary sacrificial layer between the wet etch process and the gate oxide layer. It absorbs the etching action that would otherwise directly affect the gate oxide, serving as a protective mediator during the manufacturing process.
2Manufacturing precision
If HDP oxide layer is used for trench gap-fill in the cell region, then gap-fill failure is prevented, but the process complexity increases due to different depth requirements
Solution Approach 1:
Different insulating layer configurations are applied to different regions: the cell region receives a single insulating layer configuration optimized for its smaller trench opening, while the peri region receives a dual-layer configuration optimized for its larger opening and deeper trench, allowing each region to be treated according to its specific requirements.
Solution Approach 2:
The isolation structure formation process is segmented into region-specific steps, with the peri region undergoing additional processing steps (formation and selective removal of first insulating layer) that are not required for the cell region, allowing optimized treatment for each area's unique geometric constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents gate oxide layer loss and enhances gap-fill margin, ensuring reliable formation of isolation structures in flash memory devices with varying trench depths.
Implementation Method 1
A wet etch is performed to remove at least part of the first gap-fill layer
Data Source
AI summary
A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric layer. An isolation trench is formed in the peripheral region, the isolation trench defining first and second trenches having different opening widths. A first gap-fill layer is provided over the isolation trench and on the step. The first gap-fill layer has a first portion on a sidewall of the insulating layer, a second portion on a sidewall of the gate dielectric layer, and a third portion at least partly filling the second trench of the isolation trench, the second portion being thicker than the first portion. A wet etch is performed to remove at least part of the first gap-fill layer. A second gap-fill layer is provided over the first gap-fill layer in the isolation trench to form an isolation structure. The second portion of the first gap-fill layer is configured to protect the gate dielectric layer during the wet etch step.