Flash Memory Gate Structure With L-Shaped Charge Storage
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Solution Overview
Problem
Existing flash memory devices face challenges in efficiently forming charge storage layers and spacers to enhance data retention and reliability, particularly in the fabrication process of memory cells.
Innovation Solution
The fabrication process involves forming an L-shaped charge storage layer enclosed by dielectric materials and self-aligned thin spacers along the gate structures, using controlled etching processes to create precise spacer layers and drain/source regions, ensuring isolation and protection of the memory gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used to form charge storage layers and spacers, then manufacturing simplicity is maintained, but data retention and reliability are insufficient
Solution Approach 1:
The patent applies preliminary action by forming the L-shaped charge storage layer structure before final spacer formation. The charge storage layer is deposited and patterned in advance to create the enclosed L-shaped structure that will subsequently guide spacer formation, ensuring proper alignment and charge storage capability before the actual spacer deposition occurs
Solution Approach 2:
The patent implements nesting by creating an L-shaped charge storage layer that is enclosed by dielectric materials and further enclosed by self-aligned thin spacers. The nested structure consists of the charge storage layer nested within dielectric materials, which are in turn nested within the spacer structures, creating multiple levels of enclosure that enhance charge retention while maintaining fabrication efficiency
2Manufacturing precision
If precise spacer layers are formed using controlled etching processes, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The patent applies self-service through self-aligned thin spacers where the spacer structures automatically align themselves to the gate structures during formation. The self-aligned nature eliminates the need for separate alignment steps and complex photolithography processes, achieving high precision spacer placement while maintaining fabrication throughput through the self-organizing behavior of the materials
Solution Approach 2:
The patent transitions from two-dimensional planar spacer formation to three-dimensional self-aligned spacer structures. By utilizing vertical dimensionality and the L-shaped charge storage layer geometry, the process achieves precise spacer positioning through vertical material deposition and etching rather than relying solely on planar photolithography, thereby improving precision without proportionally increasing process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the data retention and reliability of flash memory devices by improving the formation of charge storage layers and spacers, leading to more stable charge storage and efficient operation.
Implementation Method 1
Each of the memory cells may be electrically charged by injecting electrons from the substrate through the oxide layer
Implementation Method 2
a floating gate is capable of holding a charge and is separated from source and drain regions contained in a substrate by an oxide layer
Implementation Method 3
The floating gate is between the source region and the drain region, but separated from them by an oxide layer
Data Source
AI summary
A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.