Flash Memory Controller L2P Table Hash Partitioning

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The large memory requirements for logical to physical (L2P) tables in flash memory systems, particularly in SSDs, lead to increased costs due to the need for external volatile memory, necessitating a reduction in table size to minimize costs and optimize memory usage.

Innovation Solution

A method that involves calculating hash values for logical pages to determine their mapping to physical pages, using a set index and block index to partition physical pages into sets, and updating data structures to efficiently manage page writes and reads, reducing the size of each L2P entry and the overall memory needed for the L2P table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a traditional L2P table is used to map logical pages to physical pages, then the mapping functionality is provided, but the memory size required becomes very large, requiring external volatile memory and increasing system costs

Engineering Contradiction:
Improvememory size required for L2P tableVSAvoidmapping functionality
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

The patent divides the traditional L2P table into multiple smaller hash tables distributed across different memory locations. Instead of using one large centralized table, the mapping function is segmented into multiple independent hash tables that can be stored in smaller, more manageable memory portions, thereby reducing the memory burden while maintaining complete mapping functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to the mapping structure by organizing L2P entries into multiple hash tables with hierarchical addressing. The system uses a combination of hash table index and entry offset to locate mappings, effectively transitioning from a single-dimension flat table to a multi-dimensional structured approach, which reduces the contiguous memory requirement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the L2P table size is reduced to lower system costs, then memory management efficiency improves, but the complexity of managing multiple hash tables and their mappings increases

Engineering Contradiction:
Improvememory size for L2P tableVSAvoiddata structure management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The hash table structure inherently provides self-organizing capabilities through hash function computation. Each logical page address automatically maps to a specific hash table and entry position through deterministic hash computation, eliminating the need for complex external management mechanisms. The structure serves itself by using the input address to determine its own storage location.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the organizational parameter from sequential ordering to hash-based distribution. By transforming the addressing methodology from linear sequential access to distributed hash-based access, the system achieves better memory utilization with smaller table sizes while the hash function provides automatic collision resolution and location determination.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8838937B1Methods, systems and computer readable medium for writing and reading data
Publication Date: 2014.09.16 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8838937B1 patent drawing
  • US8838937B1 patent drawing
  • US8838937B1 patent drawing

AI summary

A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical address; determining to write a logical page into a selected physical page of the flash memory device; calculating a hash value for each logical page of the multiple logical pages in response to (a) a logical address of the logical page and (b) a physical page index, to provide multiple hash values of the multiple logical pages.