Flash Memory L2P Table Segmental Update Mechanism
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Solution Overview
Problem
Conventional data storage devices, particularly those using NAND flash memory, face reduced write performance due to irregular writing of updated logical-to-physical mapping tables, which affects user operation when handling large amounts of random page data.
Innovation Solution
A data storage device comprising a flash memory, dynamic random access memory (DRAM), and a memory controller that segmentally updates mapping relationships and writes updated group-mapping tables into the flash memory when the unsaved data block count exceeds a threshold, using a data scheduling ratio to manage the writing process and maintain stable performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory controller immediately writes updated group-mapping tables into the flash memory after each host write command, then the mapping relationship is kept up-to-date, but the write performance is greatly reduced due to frequent irregular writing
Solution Approach 1:
The patent segments the L2P table into multiple group-mapping tables and further divides the writing process into batched segments. Instead of writing after each host command, the controller accumulates updates in a buffer and writes in batches when the buffer reaches a threshold or periodically, reducing the frequency of write operations to the flash memory while maintaining mapping accuracy.
Solution Approach 2:
The patent implements preliminary action by buffering updated group-mapping tables in the memory controller before writing them to the flash memory. The controller pre-processes and accumulates multiple update operations, then executes them in batches, thereby reducing the number of times the flash memory is accessed for writing mapping information.
2Productivity
If the memory controller buffers all updated group-mapping tables before writing, then the write performance is improved by reducing write frequency, but the device complexity increases due to additional buffering and scheduling mechanisms
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of a buffer within the memory controller that temporarily stores updated group-mapping tables before writing them to the flash memory. This buffer acts as a mediator between the host write operations and the flash memory write operations, decoupling the frequency of host commands from the frequency of flash memory writes.
3Reliability
If the memory controller writes group-mapping tables at random intervals, then the mapping updates are reflected quickly, but the write performance fluctuates wildly affecting user operation
Solution Approach 1:
The patent implements periodic action by establishing a timer that triggers batched writing of group-mapping tables at regular intervals. This periodic mechanism ensures that mapping updates are reflected in a controlled manner while maintaining stable write performance, as the timer-based scheduling provides predictable and consistent write timing rather than random intervals.
Data Source
AI summary
A data storage device is provided. The data storage device includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping tables. The memory controller receives a host command from a host, wherein the host command includes one or more pieces of data and one or more corresponding logical addresses. The memory controller writes the data of the host command into active blocks of the flash memory. In response to the memory controller changing the active blocks into unsaved data blocks and a number of the unsaved data blocks being greater than or equal to an unsaved data block count threshold, the memory controller segmentally updates mapping relationships of the data in the unsaved data blocks, and writes the updated group-mapping tables into the flash memory.