Flash Memory Cell Programming Using Latch-Based Bit Sequencing
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Solution Overview
Problem
Conventional multi-level flash memory devices require multiple read-back operations to verify and program multi-bit data, which significantly slows down the programming process as the number of data bits increases, due to the need to determine threshold voltage distributions for each bit relative to previously written bits.
Innovation Solution
A semiconductor memory device with a plurality of latches that receive and latch each bit of write data, allowing programming of subsequent bits without the need for read-back operations by referencing previously programmed bits stored in the latches, thereby eliminating the requirement for sequential read-back operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read-back operations are performed to verify and program multi-bit data in conventional flash memory, then data accuracy is improved, but programming speed deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-latching all multi-bit data in the page buffer before programming operations begin. This allows the programming circuit to access previously programmed bit values directly from the latched data without performing intermediate read-back operations, thereby maintaining data accuracy while eliminating the time-consuming verification steps that slow down conventional programming processes
2Quantity of substance
If the number of data bits stored in a multi-level cell increases, then storage capacity is improved, but programming time increases due to more read-back operations
Solution Approach 1:
The patent addresses this contradiction by latching all multi-bit data (e.g., 2-bit, 3-bit, or more) in the page buffer before the programming operation starts. This preliminary action enables the programming circuit to sequentially program each bit while referencing previously programmed bits from the latched data, eliminating the need for multiple read-back operations and thus preventing programming time from increasing with storage capacity
Solution Approach 2:
The patent segments the programming process into sequential bit-level operations while maintaining access to all original bit values through latching. This segmentation allows each bit to be programmed in relation to previously programmed bits without requiring read-back operations, enabling high storage capacity to be achieved without proportionally increasing programming time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster multi-bit data programming by allowing each bit to be programmed in relation to previously stored bits within the latches, reducing the overall time required for programming operations and enhancing the speed of data storage.
Implementation Method 1
The cell transistor is programmed or erased using an electrical charge transfer mechanism called Fowler-Nordheim (F-N) tunneling.
Implementation Method 2
Under this erase bias condition, a strong electric field is formed between the floating gate and bulk due to a large voltage difference between these two elements, thus electrons stored on the floating gate migrate to the bulk due to the F-N tunneling effect.
Implementation Method 3
Under this program bias condition, electrons are injected onto the floating gate of the cell transistor due to the F-N tunneling effect.
Data Source
AI summary
A memory cell programming method and related semiconductor memory device are disclosed. The method involves receiving and latching first through nth bits of write data in a corresponding plurality of first through nth latches, and programming a kth bit of write data in the memory cell, where k ranges from 2 to n, in relation to first through k−1th bits of write data previously stored in the memory cell.