Configurable Latching for Asynchronous Flash Memory Timing
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Solution Overview
Problem
Asynchronous flash memory systems face critical timing issues due to the synchronous operation of ADV# and CLK signals, particularly at high clock frequencies, leading to set up and hold timing challenges in address latching mechanisms.
Innovation Solution
The memory system is configured to enable synchronous burst read mode by latching addresses on the rising edge of the clock signal with ADV# low, and a latency counter starts on the first rising clock edge with burst enable, optimizing communication between the memory controller and flash memory to mitigate timing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If addresses are latched on the rising edge of CLK with ADV# low in synchronous burst mode, then read performance and maximum frequency are improved, but timing control complexity increases
Solution Approach 1:
The patent changes the latching parameter from asynchronous to synchronous by latching addresses on the rising edge of the clock signal rather than relying on asynchronous ADV# signal transitions. This parameter change enables deterministic timing behavior that improves read performance and allows higher maximum frequencies while the increased complexity is managed through standardized timing control mechanisms.
2Ease of operation
If asynchronous page mode is used for immediate reads on power up or reset, then accessibility is improved, but read performance is limited compared to synchronous burst mode
Solution Approach 1:
The patent implements dynamic mode switching capability that allows the memory system to transition between asynchronous page mode and synchronous burst mode based on operational requirements. The system can operate in asynchronous mode for immediate accessibility on power-up or reset, then switch to synchronous burst mode for optimized read performance during normal operation, thus resolving the contradiction between ease of operation and productivity.
Data Source
AI summary
A memory, such as a flash memory, may receive a configuration bit from a memory controller to set the memory in one of two selectable modes. Thus, based on the way the memory controller operates, it can adapt the operation of the memory to suit the memory controller's techniques for entering synchronous burst read mode. In some embodiments, the bit may selectively enable the memory to assume one of two synchronous burst read modes which are based on different arrangements of CLK and ADV# signals.