Flash Memory Device Latency-Aware Update Mechanism
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Solution Overview
Problem
Traditional flash memory devices face latency and endurance issues due to the need for block-level erasure, which causes inefficiencies in data migration and invalid page management, leading to increased latency and reduced device lifespan.
Innovation Solution
A flash memory device with a novel Flash Translation Layer (FTL) incorporating a latency-aware program mechanism, latency-aware garbage collection mechanism, cyclic endurance spreading mechanism, and hot-data-aware fine-granularity mechanism, allowing for bit or page erase operations that reduce overhead and extend device endurance by optimizing update and garbage collection processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block erase operation is used, then erasure capability is achieved, but latency increases and endurance decreases
Solution Approach 1:
The patent segments the erasure operation from the block level to the page level. Instead of erasing entire blocks to free space, the system identifies and erases only the specific invalid pages that need to be freed. This segmentation allows the garbage collection process to operate more efficiently by targeting only the necessary portions of the memory block, thereby reducing both the time required for erasure and the wear on the memory cells.
2Productivity
If frequent migration and block erase are performed, then free pages are created, but latency increases and endurance issues arise
Solution Approach 1:
The system performs preliminary identification of invalid pages before executing the erasure operation. By maintaining metadata that tracks the validity status of each page, the garbage collection mechanism can immediately identify which pages are candidates for erasure without needing to scan or migrate data first. This preliminary preparation enables the system to proceed directly to the minimal necessary erasure operation, reducing latency while maintaining productivity.
3Ease of operation
If block-level operations are used, then data management is simplified, but performance and longevity are reduced
Solution Approach 1:
The patent introduces a Flash Translation Layer (FTL) that acts as an intermediary between the host system and the physical memory blocks. The FTL maintains a mapping structure that translates logical page addresses to physical block locations and tracks the validity status of each page. This intermediary layer enables fine-grained page-level management while presenting a simplified interface to the host system, thereby improving performance without sacrificing ease of operation.
Data Source
AI summary
A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.