Flash Memory LDPC Decoding with Conditional Soft-Decision ECC
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Solution Overview
Problem
The size and power consumption of nonvolatile semiconductor memory systems increase due to the large size of error correction circuits using soft-decision values for error correction in NAND-type flash memory, which affects the efficiency and accuracy of data reading.
Innovation Solution
A nonvolatile semiconductor memory system with at least one first error correction unit performing a first iterative decoding algorithm and a second error correction unit using a larger number of quantization bits for error correction, where the second unit is activated only when the first unit fails, reducing overall power consumption while maintaining high error correction ability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If soft-decision value based error correction is used, then error correction accuracy is improved, but circuit size and power consumption increase
Solution Approach 1:
The error correction function is divided into two separate units: a first error correction unit using hard-decision values for routine corrections, and a second error correction unit using soft-decision values for difficult cases. This segmentation allows the system to use the simpler, lower-power hard decision method most of the time while reserving the more accurate but power-intensive soft decision method for when it is actually needed.
Solution Approach 2:
The system changes the decision parameter from always using soft-decision values to conditionally switching between hard-decision and soft-decision values. By changing the parameter of decision value type based on correction success, the system achieves high error correction accuracy when needed while reducing power consumption during normal operation.
2Speed
If multiple error correction circuits are arranged in parallel, then reading speed is improved, but system size and power consumption increase
Solution Approach 1:
The parallel error correction architecture is segmented into two functional units with different capabilities. The first error correction unit handles the majority of cases with faster, lower-power hard decision decoding, while the second unit provides enhanced soft decision decoding for difficult cases. This segmentation allows parallel processing for speed while reducing overall power consumption compared to having all units use the more powerful soft decision method.
Solution Approach 2:
Instead of all error correction circuits performing the full soft-decision decoding process, only the necessary portion (the second unit) performs soft decision when hard decision fails. This partial application of the more intensive method reduces power consumption while maintaining the parallel architecture's speed advantages.
Data Source
AI summary
A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.